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    Searched refs:RegisterMask (Results 1 - 9 of 9) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
DispatchStage.cpp 51 const unsigned RegisterMask = PRF.isAvailable(RegDefs);
53 if (RegisterMask) {
  /src/external/apache2/llvm/dist/llvm/tools/llvm-readobj/
ARMWinEHPrinter.cpp 177 void Decoder::printRegisters(const std::pair<uint16_t, uint32_t> &RegisterMask) {
183 const uint16_t GPRMask = std::get<0>(RegisterMask);
184 const uint16_t VFPMask = std::get<1>(RegisterMask);
314 uint16_t RegisterMask = (Link << (Prologue ? 14 : 15))
317 assert((~RegisterMask & (1 << 13)) && "sp must not be set");
318 assert((~RegisterMask & (1 << (Prologue ? 15 : 14))) && "pc must not be set");
323 printRegisters(std::make_pair(RegisterMask, 0));
ARMWinEHPrinter.h 136 void printRegisters(const std::pair<uint16_t, uint32_t> &RegisterMask);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
ISDOpcodes.h 68 RegisterMask,
SelectionDAGNodes.h 2091 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2098 return N->getOpcode() == ISD::RegisterMask;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGDumper.cpp 114 case ISD::RegisterMask: return "RegisterMask";
SelectionDAGISel.cpp 2834 case ISD::RegisterMask:
SelectionDAG.cpp 625 case ISD::RegisterMask:
1970 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), None);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 3860 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3866 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3870 {ReturnAddress, Callee, RegisterMask, Chain}),

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