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    Searched refs:SDst (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIShrinkInstructions.cpp 771 const MachineOperand *SDst = TII->getNamedOperand(MI,
772 AMDGPU::OpName::sdst);
778 if (SDst) {
781 if (SDst->getReg() != VCCReg) {
782 if (SDst->getReg().isVirtual())
783 MRI.setRegAllocationHint(SDst->getReg(), 0, VCCReg);
GCNDPPCombine.cpp 126 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) {
130 if (!MRI->use_nodbg_empty(SDst->getReg()))
SIPeepholeSDWA.cpp 864 const MachineOperand *Sdst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst);
865 if (!Sdst)
867 MachineOperand *NextOp = findSingleRegUse(Sdst, MRI);
879 MachineOperand *CarryOut = TII->getNamedOperand(MISucc, AMDGPU::OpName::sdst);
935 const MachineOperand *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst);
936 if (SDst && (SDst->getReg() != AMDGPU::VCC &&
937 SDst->getReg() != AMDGPU::VCC_LO)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
AMDGPUDisassembler.cpp 639 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
643 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
644 if (SDst != -1) {
645 // VOPC - insert VCC register as sdst
647 AMDGPU::OpName::sdst);

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