| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_cik_sdma.c | 972 radeon_ring_write(ring, SH_MEM_BASES >> 2);
|
| cikd.h | 1165 #define SH_MEM_BASES 0x8C28
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| radeon_cik.c | 5537 WREG32(SH_MEM_BASES, 0);
5734 radeon_ring_write(ring, SH_MEM_BASES >> 2);
5737 radeon_ring_write(ring, 0); /* SH_MEM_BASES */
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx_v10_0.c | 1602 uint32_t sh_mem_bases; local in function:gfx_v10_0_init_compute_vmid
1610 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1617 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1755 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1757 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
|
| amdgpu_gfx_v9_0.c | 2406 uint32_t sh_mem_bases; local in function:gfx_v9_0_init_compute_vmid
2414 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2425 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
2506 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
2508 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
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