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Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_0 (Results 1 - 3 of 3) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
trinity_dpm.h	`30 #define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0)`
trinityd.h	`36 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000`
radeon_trinity_dpm.c	`601 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); 604 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); 648 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); 651 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); 653 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); 656 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); 744 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); 748 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value);`

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