HomeSort by: relevance | last modified time | path
    Searched refs:Sub2 (Results 1 - 7 of 7) sorted by relevancy

  /src/external/bsd/libc++/dist/libcxxrt/test/
test_typeinfo.cc 29 struct Sub2 : public Sub1
72 Sub2 sub2; local
76 Root *b = &sub2;
77 Root *f = &sub2;
78 Root *s2 = &sub2;
92 TEST(12 == dynamic_cast<Sub1*>(s2)->a, "Casting Sub2 -> Sub1");
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonHardwareLoops.cpp 1546 unsigned Sub2 = DI->getOperand(2).getImm();
1548 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi)
1550 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo)
HexagonBitSimplify.cpp 438 unsigned Sub1 = I.getOperand(2).getImm(), Sub2 = I.getOperand(4).getImm();
444 assert((Sub1 == SubLo && Sub2 == SubHi) || (Sub1 == SubHi && Sub2 == SubLo));
445 if (Sub1 == SubLo && Sub2 == SubHi) {
450 if (Sub1 == SubHi && Sub2 == SubLo) {
HexagonConstPropagation.cpp 1958 unsigned Sub2 = MI.getOperand(4).getImm();
1964 if (Sub2 != SubLo && Sub2 != SubHi)
1966 assert(Sub1 != Sub2);
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.cpp 1349 const CodeGenSubRegIndex *Sub2) {
1352 const RegMap &Img2 = SubRegAction.at(Sub2);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 2956 auto Sub2 = B.buildMerge(S64, {Sub2_Lo, Sub2_Hi});
2986 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Sub3, Sub2);
AMDGPUISelLowering.cpp 1901 SDValue Sub2 = DAG.getBitcast(VT,
1930 SDValue Sel2 = DAG.getSelectCC(DL, C6, Zero, Sub3, Sub2, ISD::SETNE);

Completed in 31 milliseconds