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    Searched refs:SuperReg (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.cpp 566 unsigned SuperReg = 0;
569 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
570 SuperReg = Reg;
589 // All group registers should be a subreg of SuperReg.
592 if (Reg == SuperReg) continue;
593 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
608 dbgs() << "*** Performing rename " << printReg(SuperReg, TRI)
613 // Check each possible rename register for SuperReg in round-robin
622 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 78 Register SuperReg;
113 : SuperReg(MI->getOperand(0).getReg()), MI(MI),
118 const TargetRegisterClass *RC = TRI.getPhysRegClass(SuperReg);
132 assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
133 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&
134 SuperReg != AMDGPU::EXEC && "exec should never spill");
184 RS->setRegUsed(SuperReg);
1316 assert(SpillToVGPR || (SB.SuperReg != SB.MFI.getStackPtrOffsetReg() &&
1317 SB.SuperReg != SB.MFI.getFrameOffsetReg()))
    [all...]
SIInstrInfo.h 64 MachineOperand &SuperReg,
70 MachineOperand &SuperReg,
SIInstrInfo.cpp 4531 MachineOperand &SuperReg,
4540 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
4542 .addReg(SuperReg.getReg(), 0, SubIdx);
4553 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 193 SDValue SuperReg = SDValue(Load, 0);
197 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg));
236 SDValue SuperReg = SDValue(Load, 0);
240 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg));
284 SDValue SuperReg = SDValue(Load, 0);
288 CurDAG->getTargetExtractSubreg(SubRegIdx, DL, VT, SuperReg));
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 2201 SDValue SuperReg = SDValue(VLd, 0);
2208 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2451 SDValue SuperReg;
2456 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2458 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2465 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2467 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2469 Ops.push_back(SuperReg);
2485 SuperReg = SDValue(VLdLn, 0);
2492 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 1381 SDValue SuperReg = SDValue(Ld, 0);
1384 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1417 SDValue SuperReg = SDValue(Ld, 1);
1419 ReplaceUses(SDValue(N, 0), SuperReg);
1423 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg));
1476 SDValue SuperReg = SDValue(Load, 0);
1479 AArch64::zsub0 + i, DL, VT, SuperReg));
1628 SDValue SuperReg = SDValue(Ld, 0);
1634 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg);
1677 SDValue SuperReg = SDValue(Ld, 1)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp 1690 MCRegister SuperReg =
1693 if (VSXSelfCopyCrash && SrcReg == SuperReg)
1696 DestReg = SuperReg;
1699 MCRegister SuperReg =
1702 if (VSXSelfCopyCrash && DestReg == SuperReg)
1705 SrcReg = SuperReg;

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