| /src/external/gpl3/gcc.old/dist/gcc/config/riscv/ |
| riscv-ftypes.def | 29 DEF_RISCV_FTYPE (0, (USI))
30 DEF_RISCV_FTYPE (1, (VOID, USI))
|
| /src/external/gpl3/gcc/dist/gcc/config/riscv/ |
| riscv-ftypes.def | 29 DEF_RISCV_FTYPE (0, (USI))
31 DEF_RISCV_FTYPE (1, (VOID, USI))
33 DEF_RISCV_FTYPE (1, (USI, VOID_PTR))
34 DEF_RISCV_FTYPE (1, (USI, USI))
36 DEF_RISCV_FTYPE (1, (USI, UQI))
37 DEF_RISCV_FTYPE (1, (USI, UHI))
40 DEF_RISCV_FTYPE (2, (USI, UQI, UQI))
41 DEF_RISCV_FTYPE (2, (USI, USI, UHI)
[all...] |
| /src/external/gpl3/gcc.old/dist/gcc/config/loongarch/ |
| loongarch-ftypes.def | 39 DEF_LARCH_FTYPE (1, (UQI, USI))
40 DEF_LARCH_FTYPE (1, (UHI, USI))
41 DEF_LARCH_FTYPE (1, (USI, USI))
42 DEF_LARCH_FTYPE (1, (UDI, USI))
43 DEF_LARCH_FTYPE (1, (USI, UQI))
44 DEF_LARCH_FTYPE (1, (VOID, USI))
46 DEF_LARCH_FTYPE (2, (VOID, UQI, USI))
47 DEF_LARCH_FTYPE (2, (VOID, UHI, USI))
48 DEF_LARCH_FTYPE (2, (VOID, USI, USI)
[all...] |
| /src/external/gpl3/gdb/dist/sim/or1k/ |
| cpu.c | 33 USI
42 or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
49 USI
58 or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
65 USI
74 or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
129 USI
138 or1k32bf_h_sys_vr_set (SIM_CPU *current_cpu, USI newval)
145 USI
154 or1k32bf_h_sys_upr_set (SIM_CPU *current_cpu, USI newval
[all...] |
| or1k-sim.h | 59 void or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
60 const USI or1k_upr, const USI or1k_cpucfgr);
65 void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum);
67 void or1k32bf_nop (sim_cpu *current_cpu, USI uimm16);
68 USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr);
69 void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
[all...] |
| arch.h | 31 #define UWI USI
32 #define AI USI
34 #define IAI USI
|
| cpu.h | 46 USI h_pc;
56 USI h_gpr[32];
3258 USI or1k32bf_h_pc_get (SIM_CPU *);
3259 void or1k32bf_h_pc_set (SIM_CPU *, USI);
3260 USI or1k32bf_h_spr_get (SIM_CPU *, UINT);
3261 void or1k32bf_h_spr_set (SIM_CPU *, UINT, USI);
3262 USI or1k32bf_h_gpr_get (SIM_CPU *, UINT);
3263 void or1k32bf_h_gpr_set (SIM_CPU *, UINT, USI);
3270 USI or1k32bf_h_sys_vr_get (SIM_CPU *);
3271 void or1k32bf_h_sys_vr_set (SIM_CPU *, USI);
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/or1k/ |
| cpu.c | 33 USI
42 or1k32bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
49 USI
58 or1k32bf_h_spr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
65 USI
74 or1k32bf_h_gpr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
129 USI
138 or1k32bf_h_sys_vr_set (SIM_CPU *current_cpu, USI newval)
145 USI
154 or1k32bf_h_sys_upr_set (SIM_CPU *current_cpu, USI newval
[all...] |
| or1k-sim.h | 59 void or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr,
60 const USI or1k_upr, const USI or1k_cpucfgr);
65 void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum);
67 void or1k32bf_nop (sim_cpu *current_cpu, USI uimm16);
68 USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr);
69 void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
[all...] |
| arch.h | 31 #define UWI USI
32 #define AI USI
34 #define IAI USI
|
| cpu.h | 46 USI h_pc;
56 USI h_gpr[32];
3248 USI or1k32bf_h_pc_get (SIM_CPU *);
3249 void or1k32bf_h_pc_set (SIM_CPU *, USI);
3250 USI or1k32bf_h_spr_get (SIM_CPU *, UINT);
3251 void or1k32bf_h_spr_set (SIM_CPU *, UINT, USI);
3252 USI or1k32bf_h_gpr_get (SIM_CPU *, UINT);
3253 void or1k32bf_h_gpr_set (SIM_CPU *, UINT, USI);
3260 USI or1k32bf_h_sys_vr_get (SIM_CPU *);
3261 void or1k32bf_h_sys_vr_set (SIM_CPU *, USI);
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/lm32/ |
| sim-main.h | 62 extern USI lm32bf_b_insn (SIM_CPU * current_cpu, USI r0, USI f_r0);
63 extern USI lm32bf_divu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2);
64 extern USI lm32bf_modu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
[all...] |
| arch.h | 31 #define UWI USI
32 #define AI USI
34 #define IAI USI
|
| /src/external/gpl3/gdb/dist/sim/lm32/ |
| sim-main.h | 62 extern USI lm32bf_b_insn (SIM_CPU * current_cpu, USI r0, USI f_r0);
63 extern USI lm32bf_divu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2);
64 extern USI lm32bf_modu_insn (SIM_CPU * current_cpu, IADDR pc, USI r0, USI r1, USI r2)
[all...] |
| arch.h | 31 #define UWI USI
32 #define AI USI
34 #define IAI USI
|
| /src/external/gpl3/gdb.old/dist/sim/iq2000/ |
| arch.h | 31 #define UWI USI
32 #define AI USI
34 #define IAI USI
|
| /src/external/gpl3/gdb/dist/sim/iq2000/ |
| arch.h | 31 #define UWI USI
32 #define AI USI
34 #define IAI USI
|
| /src/external/gpl3/gdb.old/dist/sim/cris/ |
| sim-main.h | 42 USI addr;
61 USI priority;
65 USI altstack;
66 USI options;
88 USI last_execution;
120 USI endmem;
121 USI endbrk;
122 USI stack_low;
130 USI syscalls;
151 USI sighandler[64]
[all...] |
| cris-sim.h | 30 USI branch_taken;
33 USI old_pc;
82 extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI);
83 extern USI crisv10f_break_handler (SIM_CPU *, USI, USI);
84 extern USI crisv32f_break_handler (SIM_CPU *, USI, USI);
85 extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI
[all...] |
| /src/external/gpl3/gdb/dist/sim/cris/ |
| sim-main.h | 42 USI addr;
61 USI priority;
65 USI altstack;
66 USI options;
88 USI last_execution;
120 USI endmem;
121 USI endbrk;
122 USI stack_low;
130 USI syscalls;
151 USI sighandler[64]
[all...] |
| cris-sim.h | 30 USI branch_taken;
33 USI old_pc;
82 extern void cris_flush_simulator_decode_cache (SIM_CPU *, USI);
83 extern USI crisv10f_break_handler (SIM_CPU *, USI, USI);
84 extern USI crisv32f_break_handler (SIM_CPU *, USI, USI);
85 extern USI cris_break_13_handler (SIM_CPU *, USI, USI, USI, USI, USI, USI
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/frv/ |
| registers.h | 31 USI init_value; /* initial value */
32 USI reset_value; /* value for software reset */
33 USI reset_mask; /* bits which are reset */
34 USI read_only_mask; /* bits which are read-only */
|
| /src/external/gpl3/gdb/dist/sim/frv/ |
| registers.h | 31 USI init_value; /* initial value */
32 USI reset_value; /* value for software reset */
33 USI reset_mask; /* bits which are reset */
34 USI read_only_mask; /* bits which are read-only */
|
| /src/external/gpl3/binutils/dist/include/cgen/ |
| basic-modes.h | 39 typedef uint32_t USI;
48 #define MAKEDI(hi, lo) ((((DI) (SI) (hi)) << 32) | ((UDI) (USI) (lo)))
|
| /src/external/gpl3/binutils.old/dist/include/cgen/ |
| basic-modes.h | 39 typedef uint32_t USI;
48 #define MAKEDI(hi, lo) ((((DI) (SI) (hi)) << 32) | ((UDI) (USI) (lo)))
|
