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    Searched refs:WREG32_OR (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_r600_hdmi.c 236 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
239 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
350 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset,
371 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
404 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
458 WREG32_OR(HDMI0_CONTROL + offset,
466 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
492 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
500 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
508 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN)
    [all...]
radeon_dce3_1_afmt.c 220 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,
224 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,
234 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);
radeon_evergreen_hdmi.c 389 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
400 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);
424 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
463 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,
radeon_evergreen.c 1755 WREG32_OR(DC_HPDx_INT_CONTROL(hpd), DC_HPDx_INT_POLARITY);
4651 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK);
4656 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK);
4661 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i],
radeon_si.c 6187 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK);
6192 WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK);
radeon.h 2629 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v3_0.c 543 WREG32_OR(mmVCE_VCPU_CNTL, 0x00100000);
amdgpu.h 1088 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
amdgpu_dce_v8_0.c 1663 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset,
1671 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset,

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