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    Searched refs:buildAnyExt (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsLegalizerInfo.cpp 370 Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0);
372 Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0);
MipsCallLowering.cpp 302 return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUPostLegalizerCombiner.cpp 242 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0);
AMDGPUCallLowering.cpp 38 return Handler.MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);
AMDGPULegalizerInfo.cpp 3593 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0));
3644 Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
InlineAsmLowering.cpp 266 Src = MIRBuilder.buildAnyExt(LLT::scalar(DstSize), Src).getReg(0);
CallLowering.cpp 472 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
1075 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
LegalizerHelper.cpp 805 MIRBuilder.buildAnyExt(DstReg, ImplicitReg);
906 MIRBuilder.buildAnyExt(DstReg, TmpReg);
1527 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0);
1556 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0);
1662 Src = MIRBuilder.buildAnyExt(WideTy, Src);
1809 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1));
1811 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2));
2829 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
MachineIRBuilder.cpp 416 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MachineIRBuilder.h 602 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);

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