| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/ |
| amdgpu_dce110_clk_mgr.c | 188 context->bw_ctx.bw.dce.all_displays_in_sync;
190 context->bw_ctx.bw.dce.nbp_state_change_enable == false;
192 context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
194 context->bw_ctx.bw.dce.cpup_state_change_enable == false;
196 context->bw_ctx.bw.dce.blackout_recovery_time_us;
209 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
215 context->bw_ctx.bw.dce.sclk_khz);
228 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
259 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
274 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk)
[all...] |
| /src/sys/dev/ic/ |
| ld_aac.c | 176 struct aac_blockwrite *bw; local in function:ld_aac_dobio
182 bw = (struct aac_blockwrite *)&fib->data[0];
183 bw->Command = htole32(VM_CtBlockWrite);
184 bw->ContainerId = htole32(sc->sc_hwunit);
185 bw->BlockNumber = htole32(blkno);
186 bw->ByteCount = htole32(datasize);
187 bw->Stable = htole32(CUNSTABLE);
191 sgt = &bw->SgMap;
221 struct aac_blockwrite64 *bw; local in function:ld_aac_dobio
227 bw = (struct aac_blockwrite64 *)&fib->data[0]
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_debug.c | 357 context->bw_ctx.bw.dcn.clk.dispclk_khz,
358 context->bw_ctx.bw.dcn.clk.dppclk_khz,
359 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
360 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
361 context->bw_ctx.bw.dcn.clk.fclk_khz,
362 context->bw_ctx.bw.dcn.clk.socclk_khz);
365 context->bw_ctx.bw.dcn.clk.dispclk_khz,
366 context->bw_ctx.bw.dcn.clk.dppclk_khz,
367 context->bw_ctx.bw.dcn.clk.dcfclk_khz,
368 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz
[all...] |
| /src/usr.sbin/wakeonlan/ |
| wakeonlan.c | 167 ssize_t bw, len; local in function:send_wakeup
178 bw = 0;
180 if ((bw = write(bpf, p, len)) == -1)
182 len -= bw;
183 p += bw;
|
| /src/games/gomoku/ |
| bdisp.c | 124 int bw = (int)strlen(plyr[BLACK]); local in function:bdwho
128 int total = fixed + bw + ww;
137 if (bw <= half)
138 ww = remaining - bw;
140 bw = remaining - ww;
142 bw = half, ww = remaining - half;
148 bw, plyr[BLACK], ww, plyr[WHITE]);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_resource.c | 958 &context->bw_ctx.bw.dce))
968 if (memcmp(&dc->current_state->bw_ctx.bw.dce,
969 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
983 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
984 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
985 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
986 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
987 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
988 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| amdgpu_dce112_resource.c | 879 &context->bw_ctx.bw.dce))
887 if (memcmp(&dc->current_state->bw_ctx.bw.dce,
888 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) {
902 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark,
903 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark,
904 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark,
905 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark,
906 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark,
907 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark
[all...] |
| /src/sys/dev/pci/ixgbe/ |
| ixgbe_dcb.c | 51 * @bw: bandwidth index by traffic class
56 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
67 if (bw[i] < min_percent && bw[i])
68 min_percent = bw[i];
75 int val = uimin(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
81 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
317 u8 i, j, bw = 0, bw_id; local in function:ixgbe_dcb_check_config_cee
330 bw = p->bwg_percent
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 103 /* BW depend on FCLK, MCLK, # of channels */
104 /* dual channel BW */
109 /* single channel BW
555 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
557 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
559 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
561 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
562 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
569 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
571 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns
[all...] |
| /src/dist/pf/sbin/pfctl/ |
| pfctl_altq.c | 146 print_altq(const struct pf_altq *a, unsigned level, struct node_queue_bw *bw,
150 print_queue(a, level, bw, 1, qopts);
171 if (bw != NULL && bw->bw_percent > 0) {
172 if (bw->bw_percent < 100)
173 printf("bandwidth %u%% ", bw->bw_percent);
183 print_queue(const struct pf_altq *a, unsigned level, struct node_queue_bw *bw,
195 if (bw != NULL && bw->bw_percent > 0) {
196 if (bw->bw_percent < 100
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| dce_clk_mgr.c | 232 if (context->bw_ctx.bw.dce.dispclk_khz >
242 < context->bw_ctx.bw.dce.dispclk_khz)
620 context->bw_ctx.bw.dce.all_displays_in_sync;
622 context->bw_ctx.bw.dce.nbp_state_change_enable == false;
624 context->bw_ctx.bw.dce.cpuc_state_change_enable == false;
626 context->bw_ctx.bw.dce.cpup_state_change_enable == false;
628 context->bw_ctx.bw.dce.blackout_recovery_time_us;
630 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
635 context->bw_ctx.bw.dce.sclk_khz);
648 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/ |
| amdgpu_dcn20_clk_mgr.c | 121 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
123 prev_dppclk_khz = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
156 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
263 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
282 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
388 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
391 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz;
394 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
397 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz;
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_dp.c | 241 ior->dp.nr, ior->dp.bw * 27);
251 while ((ior->dp.bw * 2700) < nvbios_rd16(bios, lnkcmp))
255 while (ior->dp.bw < nvbios_rd08(bios, lnkcmp))
279 sink[0] = ior->dp.bw;
336 u8 bw; member in struct:dp_rates
375 if (cfg->nr <= outp_nr && cfg->bw <= outp_bw) {
380 (cfg->nr <= sink_nr && cfg->bw <= sink_bw))
402 failsafe->nr, failsafe->bw * 27);
406 if ((cfg->nr > outp_nr || cfg->bw > outp_bw ||
407 cfg->nr > sink_nr || cfg->bw > sink_bw))
[all...] |
| nouveau_nvkm_engine_disp_sortu102.c | 51 clksor |= sor->dp.bw << 18;
|
| nouveau_nvkm_engine_disp_piornv50.c | 46 int ret = nvkm_i2c_aux_lnk_ctl(aux, pior->dp.nr, pior->dp.bw,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_resource.c | 2061 * bw calculations due to cursor on/off
2254 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2728 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2729 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2730 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2731 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2732 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2733 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2734 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2735 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1 (…)
[all...] |
| /src/sbin/newfs_lfs/ |
| newfs.c | 116 off_t off, bw; local in function:auto_segsize
133 bw = off / (finish - start);
151 printf("bw = %ld B/s, seek time %ld ms (%ld seeks/s)\n",
152 (long)bw, 1000/seeks, seeks);
153 final = dbtob(btodb(4 * bw / seeks));
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_bw.c | 221 int ct, bw; local in function:icl_get_bw_info
231 bw = icl_calc_bw(sp->dclk, clpchgroup * 32 * num_channels, ct);
234 bw * 9 / 10); /* 90% */
236 DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
286 * Any bw group has same amount of QGV points
299 unsigned int bw = icl_max_bw(dev_priv, num_planes, i); local in function:intel_max_data_rate
301 min_bw = min(bw, min_bw);
418 * Avoid locking the bw state when
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 480 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz,
481 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz,
482 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz,
483 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
484 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz,
485 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce100/ |
| amdgpu_dce_clk_mgr.c | 213 if (context->bw_ctx.bw.dce.dispclk_khz >
223 < context->bw_ctx.bw.dce.dispclk_khz)
406 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
| /src/sys/dev/vme/ |
| xyreg.h | 140 volatile u_char bw:1; /* byte(1)/word(0) xfer size */ member in struct:xy_iopb
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce120/ |
| amdgpu_dce120_clk_mgr.c | 96 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
|
| /src/sys/arch/sun3/dev/ |
| xyreg.h | 141 volatile u_char bw:1; /* byte(1)/word(0) xfer size */ member in struct:xy_iopb
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 256 struct dcn_fe_bandwidth bw; member in struct:plane_resource
349 union bw_output bw; member in struct:bw_context
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/i2c/ |
| nouveau_nvkm_subdev_i2c_aux.c | 151 nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *aux, int nr, int bw, bool ef)
154 return aux->func->lnk_ctl(aux, nr, bw, ef);
|
