/src/sys/arch/arm/imx/ |
imxspi.c | 295 uint32_t chipselect; local in function:imxspi_sched 310 chipselect = READ_REG(sc, CONREG); 311 chipselect &= ~IMXSPI_TYPE(CON_CS); 312 chipselect |= __SHIFTIN(st->st_slave, IMXSPI_TYPE(CON_CS)); 313 WRITE_REG(sc, CONREG, chipselect);
|
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
keystone-k2e-evm.dts | 94 ti,cs-chipselect = <0>; 111 ti,davinci-chipselect = <0>;
|
keystone-k2l-evm.dts | 67 ti,cs-chipselect = <0>; 84 ti,davinci-chipselect = <0>;
|
keystone-k2hk-evm.dts | 111 ti,cs-chipselect = <0>; 128 ti,davinci-chipselect = <0>;
|
imx6qdl-dfi-fs700-m60.dtsi | 152 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
|
da850-evm.dts | 425 ti,cs-chipselect = <3>; 434 ti,davinci-chipselect = <1>;
|
da850-lcdk.dts | 344 ti,cs-chipselect = <3>; 353 ti,davinci-chipselect = <1>;
|
vexpress-v2m-rs1.dtsi | 159 #address-cells = <2>; /* SMB chipselect number and offset */
|
vexpress-v2m.dtsi | 80 #address-cells = <2>; /* SMB chipselect number and offset */
|
qcom-apq8060-dragonboard.dts | 583 * SLOW chipselect config
|
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/arm/ |
foundation-v8.dtsi | 118 #address-cells = <2>; /* SMB chipselect number and offset */
|
rtsm_ve-motherboard.dtsi | 87 #address-cells = <2>; /* SMB chipselect number and offset */
|
vexpress-v2m-rs1.dtsi | 159 #address-cells = <2>; /* SMB chipselect number and offset */
|