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  /src/sys/arch/arm/broadcom/
bcm2835_cm.c 207 bcm_cm_get(enum bcm_cm_clock clk, uint32_t *ctlp, uint32_t *divp)
245 if (divp != NULL)
246 *divp = CM_READ(sc, divreg);
  /src/sys/arch/arm/nvidia/
tegra210_car.c 1147 u_int divm, divn, divp; local
1162 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;
1164 /* XXX divp is not applied to PLLP's primary output */
1165 divp = 0;
1167 divp = 0;
1170 divp = __SHIFTOUT(base, tpll->divp_mask);
1174 return rate / (divm << divp);
1197 const u_int divp = 0; local
1214 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);
tegra124_car.c 1025 u_int divm, divn, divp; local
1040 divp = __SHIFTOUT(base, tpll->divp_mask) ? 0 : 1;
1042 divp = __SHIFTOUT(base, tpll->divp_mask);
1046 return rate / (divm << divp);
1069 const u_int divp = 0; local
1086 base |= __SHIFTIN(divp, CAR_PLLX_BASE_DIVP);
tegra124_cpu.c 88 u_int divp; member in struct:tegra124_cpufreq_rate
  /src/sys/dev/sdmmc/
sdhc.c 1019 sdhc_clock_divisor(struct sdhc_host *hp, u_int freq, u_int *divp)
1026 *divp = SDHC_SDCLK_CGM
1042 *divp = (div << SDHC_SDCLK_DIV_SHIFT)
1062 *divp = div << (ffs(hp->sc->sc_clkmsk) - 1);
1071 *divp = (((div >> 8) & SDHC_SDCLK_XDIV_MASK)
1080 *divp = (div / 2) << SDHC_SDCLK_DIV_SHIFT;
  /src/sys/arch/vax/vax/
emulate.S 1210 /* 24 */ EMULATE(cvtpt); EMULATE(mulp); EMULATE(cvttp); EMULATE(divp)

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