| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/therm/ |
| nouveau_nvkm_subdev_therm_fanpwm.c | 49 u32 divs, duty; local
52 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty);
53 if (ret == 0 && divs) {
54 divs = max(divs, duty);
56 duty = divs - duty;
57 return (duty * 100) / divs;
68 u32 divs, duty; local
71 divs = fan->base.perf.pwm_divisor;
73 divs = 1
96 u32 divs, duty; local
[all...] |
| nouveau_nvkm_subdev_therm_gm107.c | 39 gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
42 *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff;
48 gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
51 nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */
|
| nouveau_nvkm_subdev_therm_gf119.c | 72 gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
80 *divs = nvkm_rd32(device, 0x00e114 + (indx * 8));
85 *divs = nvkm_rd32(device, 0x0200d8) & 0x1fff;
94 gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
101 nvkm_wr32(device, 0x00e114 + (indx * 8), divs);
104 nvkm_mask(device, 0x0200d8, 0x1fff, divs); /* keep the high bits */
|
| nouveau_nvkm_subdev_therm_nv40.c | 126 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
134 *divs = (reg & 0x00007fff);
141 *divs = nvkm_rd32(device, 0x0015f8);
154 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
159 nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);
162 nvkm_wr32(device, 0x0015f8, divs);
|
| nouveau_nvkm_subdev_therm_nv50.c | 71 nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
79 *divs = nvkm_rd32(device, 0x00e114 + (id * 8));
88 nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
95 nvkm_wr32(device, 0x00e114 + (id * 8), divs);
|
| /src/sys/arch/arm/rockchip/ |
| rk_cru_arm.c | 57 const uint32_t val = CRU_READ(sc, arm->divs[0].reg);
58 const u_int div = __SHIFTOUT(val, arm->divs[0].mask) + 1;
102 for (int i = 0; i < __arraycount(arm->divs); i++) {
103 if (arm->divs[i].reg == 0 && arm->divs[i].mask == 0)
106 const uint32_t write_mask = arm->divs[i].mask << 16;
108 arm->divs[i].mask);
109 CRU_WRITE(sc, arm->divs[i].reg, write_mask | write_val);
157 for (int i = 0; i < __arraycount(cpu_rate->divs); i++) {
158 if (cpu_rate->divs[i].reg == 0 && cpu_rate->divs[i].mask == 0 &
[all...] |
| rk_cru.h | 161 struct rk_regmaskval divs[4]; member in struct:rk_cru_cpu_rate
176 struct rk_regmask divs[4]; member in struct:rk_cru_arm
202 .u.arm.divs[0].reg = (_reg), \
203 .u.arm.divs[0].mask = (_div_mask), \
236 .u.arm.divs[0].reg = (_div_reg), \
237 .u.arm.divs[0].mask = (_div_mask), \
248 .u.arm.divs[0].reg = (_div0_reg), \
249 .u.arm.divs[0].mask = (_div0_mask), \
250 .u.arm.divs[1].reg = (_div1_reg), \
251 .u.arm.divs[1].mask = (_div1_mask),
[all...] |
| rk3399_cru.c | 149 .divs[0] = { .reg = (_reg0), .mask = (_reg0_mask), .val = (_reg0_val) },\
150 .divs[1] = { .reg = (_reg1), .mask = (_reg1_mask), .val = (_reg1_val) },\
|
| rk3588_cru.c | 131 .divs = { \
195 .divs[0] = { \
204 .divs[1] = { \
|
| /src/external/gpl3/gdb/dist/sim/testsuite/h8300/ |
| div.s | 1 # Hitachi H8 testcase 'divs', 'divu', 'divxs', 'divxu'
19 ;; divs.w rs, rd
23 divs.w r2, r1
43 ;; divs.w xx:4, rd
46 divs.w #2:4, r1
66 ;; divs.l ers, erd
70 divs.l er2, er1
90 ;; divs.l xx:4, rd
93 divs.l #2:4, er1
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/h8300/ |
| div.s | 1 # Hitachi H8 testcase 'divs', 'divu', 'divxs', 'divxu'
19 ;; divs.w rs, rd
23 divs.w r2, r1
43 ;; divs.w xx:4, rd
46 divs.w #2:4, r1
66 ;; divs.l ers, erd
70 divs.l er2, er1
90 ;; divs.l xx:4, rd
93 divs.l #2:4, er1
|
| /src/external/gpl3/gdb/dist/sim/testsuite/sh/ |
| div.s | 1 # sh testcase for divs and divu
13 divs r0, r1
33 divs r0, r1
53 divs r0, r1
73 divs r0, r1
96 divs r0, r1
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/sh/ |
| div.s | 1 # sh testcase for divs and divu
13 divs r0, r1
33 divs r0, r1
53 divs r0, r1
73 divs r0, r1
96 divs r0, r1
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| nouveau_nvkm_subdev_clk_mcp77.c | 217 int divs = 0; local
221 out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs);
228 clk->cctrl = divs << 16;
252 out = calc_P((core << 1), shader, &divs);
256 (divs + P2) <= 7) {
258 clk->sctrl = (divs + P2) << 16;
267 out = calc_P(core, vdec, &divs);
271 clk->vdiv = divs << 16;
|
| nouveau_nvkm_subdev_clk_nv50.c | 452 clk_mask(hwsq, divs, divsm, divsv);
|
| /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.disasm/ |
| t06_ari2.s | 180 divs.w #0xf:4,r1 ;01d651f1
182 divs.w r3,r1 ;01d25131
184 divs.l #0xf:4,er1 ;01d653f1
186 divs.l er3,er1 ;01d25331
|
| /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.disasm/ |
| t06_ari2.s | 180 divs.w #0xf:4,r1 ;01d651f1
182 divs.w r3,r1 ;01d25131
184 divs.l #0xf:4,er1 ;01d653f1
186 divs.l er3,er1 ;01d25331
|
| /src/sys/arch/sgimips/dev/ |
| scn.c | 358 } divs[] = { variable in typeref:struct:__anon1866
365 #define DIVS (sizeof(divs)/sizeof(divs[0]))
492 #ifdef DIVS
496 for (i = 0; i < DIVS && divs[i].speed <= dp->counter; i++) {
497 if (divs[i].speed == dp->counter) {
498 div = divs[i].div;
|
| /src/sys/dev/ |
| sequencer.c | 1193 seq_timer_waitabs(struct sequencer_softc *sc, uint32_t divs)
1203 t->divs_lastevent = divs;
1204 divs -= t->divs_lastchange;
1205 usec = (long long)divs * (long long)t->usperdiv; /* convert to usec */
1209 divs, when.tv_sec, (uint64_t)when.tv_usec));
|
| /src/sys/arch/m68k/060sp/dist/ |
| ilsp.s | 115 # divs.l #
205 tst.b POSNEG(%a6) # do divs, divu separately
208 # it was a divs.l, so ccode setting is a little more complicated...
|
| itest.s | 1144 divs.l %d1,%d2:%d3
1166 divs.l %d1,%d2:%d3
1190 divs.l %d1,%d2:%d3
|
| /src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| divq.s | 25 divs (r0, r1);
|
| /src/external/gpl3/gdb.old/dist/sim/testsuite/bfin/ |
| divq.s | 25 divs (r0, r1);
|
| /src/external/gpl3/gdb/dist/sim/bfin/ |
| bfin-sim.c | 1161 /* DIVS ( Dreg, Dreg ) ;
1166 divs (SIM_CPU *cpu, bu32 pquo, bu16 divisor) function
2615 TRACE_INSN (cpu, "DIVS ( R%i, R%i );", dst, src);
2616 SET_DREG (dst, divs (cpu, DREG (dst), (bu16)DREG (src)));
|
| /src/external/gpl3/gdb.old/dist/sim/bfin/ |
| bfin-sim.c | 1161 /* DIVS ( Dreg, Dreg ) ;
1166 divs (SIM_CPU *cpu, bu32 pquo, bu16 divisor) function
2615 TRACE_INSN (cpu, "DIVS ( R%i, R%i );", dst, src);
2616 SET_DREG (dst, divs (cpu, DREG (dst), (bu16)DREG (src)));
|
