| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_display_rq_dlg_helpers.c | 318 "DML_RQ_DLG_CALC: dst_y_delta_drq_limit = 0x%0x\n",
319 dlg_regs.dst_y_delta_drq_limit);
|
| display_mode_structs.h | 463 unsigned int dst_y_delta_drq_limit; member in struct:_vcs_dpi_display_dlg_regs_st
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_hw_sequencer_debug.c | 280 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
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| amdgpu_dcn10_hw_sequencer.c | 247 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 1526 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1528 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
|
| amdgpu_display_rq_dlg_calc_20v2.c | 1527 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1529 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 1626 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1628 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
|
