| /src/sys/arch/arm/ep93xx/ |
| epsoc.c | 79 uint64_t fclk, pclk, hclk; local
136 fclk = 14745600ULL * ((pll1x1fbd1 + 1) * (pll1x2fbd2 + 1)) /
138 hclk = fclk / hclkdivisors[hclkdiv];
142 fclk = fclk >> fclkdiv;
144 fclk = 14745600ULL;
146 printf("%s: fclk %lld.%02lld MHz hclk %lld.%02lld MHz pclk %lld.%02lld MHz\n",
148 fclk / 1000000, (fclk % 1000000 + 5000) / 10000,
152 sc->sc_fclk = fclk;
[all...] |
| /src/sys/dev/fdt/ |
| fixedfactorclock.c | 163 struct fixedfactorclock_clk *fclk = (struct fixedfactorclock_clk *)clk; local
170 return (clk_get_rate(clkp_parent) * fclk->mult) / fclk->div;
|
| fixedclock.c | 153 struct fixedclock_clk *fclk = (struct fixedclock_clk *)clk; local
155 return fclk->rate;
|
| /src/sys/arch/evbarm/stand/boot2440/ |
| main.c | 80 static void s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk,
112 int fclk, hclk; local
133 Target FCLK is 405MHz, and we assume an input crystal of 12MHz
146 s3c24x0_clock_freq2(S3C2440_CLKMAN_BASE, &fclk, &hclk, &pclk);
408 s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
429 /* 00b: HCLK = FCLK/1*/
432 /* 01b: HCLK = FCLK/2*/
436 /* 10b: HCLK = FCLK/4 when CAMDIVN[9] (HCLK4_HALF) = 0
437 * HCLK = FCLK/8 when CAMDIVN[9] (HCLK4_HALF) = 1 */
444 /* 11b: HCLK = FCLK/3 when CAMDIVN[8] (HCLK3_HALF) =
[all...] |
| /src/sys/arch/arm/s3c2xx0/ |
| s3c2410.c | 155 aprint_normal(": fclk %d MHz hclk %d MHz pclk %d MHz\n",
206 s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
227 if (fclk) *fclk = f;
|
| s3c2440.c | 185 aprint_normal(": fclk %d MHz hclk %d MHz pclk %d MHz\n",
238 s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
259 /* 00b: HCLK = FCLK/1*/
262 /* 01b: HCLK = FCLK/2*/
266 /* 10b: HCLK = FCLK/4 when CAMDIVN[9] (HCLK4_HALF) = 0
267 * HCLK = FCLK/8 when CAMDIVN[9] (HCLK4_HALF) = 1 */
274 /* 11b: HCLK = FCLK/3 when CAMDIVN[8] (HCLK3_HALF) = 0
275 * HCLK = FCLK/6 when CAMDIVN[8] (HCLK3_HALF) = 1 */
288 if (fclk) *fclk = f
[all...] |
| s3c2800.c | 149 aprint_normal(": fclk %d MHz hclk %d MHz pclk %d MHz\n",
205 s3c2800_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
226 if (fclk) *fclk = f;
|
| /src/sys/arch/arm/arm32/ |
| cpu.c | 215 char *fclk; local
221 fclk = "bus clock";
224 fclk = "ref clock";
227 fclk = "pll";
230 fclk = "illegal";
233 aprint_normal(" fclk source=%s\n", fclk);
|
| /src/sys/arch/arm/footbridge/ |
| dc21285reg.h | 283 #define UART_BRD(fclk, x) (((fclk) / 4 / 16 / x) - 1)
393 #ifndef FCLK
394 #define FCLK 50000000
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| amdgpu_smu.h | 229 uint32_t fclk; member in struct:smu_bios_boot_up_values
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| amdgpu_smu_v11_0.c | 658 smu->smu_table.boot_values.fclk = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
|
| amdgpu_arcturus_ppt.c | 141 CLK_MAP(FCLK, PPCLK_FCLK),
476 /* fclk */
482 pr_err("[SetupDefaultDpmTable] failed to get fclk dpm levels!");
487 single_dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
713 pr_err("Attempt to get current fclk Failed!");
720 pr_err("Attempt to get fclk levels Failed!");
844 * support mclk/socclk/fclk softmin/softmax settings
|
