| /src/external/gpl3/binutils/dist/include/opcode/ |
| wasm.h | 57 WASM_OPCODE (0x29, "i64.load", i32, i64, load, agnostic)
64 WASM_OPCODE (0x30, "i64.load8_s", i32, i64, load, signed)
65 WASM_OPCODE (0x31, "i64.load8_u", i32, i64, load, unsigned)
66 WASM_OPCODE (0x32, "i64.load16_s", i32, i64, load, signed)
67 WASM_OPCODE (0x33, "i64.load16_u", i32, i64, load, unsigned
[all...] |
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| wasm.h | 57 WASM_OPCODE (0x29, "i64.load", i32, i64, load, agnostic)
64 WASM_OPCODE (0x30, "i64.load8_s", i32, i64, load, signed)
65 WASM_OPCODE (0x31, "i64.load8_u", i32, i64, load, unsigned)
66 WASM_OPCODE (0x32, "i64.load16_s", i32, i64, load, signed)
67 WASM_OPCODE (0x33, "i64.load16_u", i32, i64, load, unsigned
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFSelectionDAGInfo.cpp | 38 DAG.getConstant(CopyLen, dl, MVT::i64),
39 DAG.getConstant(Alignment.value(), dl, MVT::i64));
|
| BPFISelLowering.cpp | 61 addRegisterClass(MVT::i64, &BPF::GPRRegClass);
70 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
75 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
77 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
99 for (auto VT : { MVT::i32, MVT::i64 }) {
129 setOperationAction(ISD::CTTZ, MVT::i64, Custom);
130 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
131 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
132 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
331 case MVT::i64
[all...] |
| BPFISelDAGToDAG.cpp | 104 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
105 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64);
121 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
125 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
131 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64);
149 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
153 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
217 SDValue R6Reg = CurDAG->getRegister(BPF::R6, MVT::i64);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblySelectionDAGInfo.cpp | 30 auto LenMVT = ST.hasAddr64() ? MVT::i64 : MVT::i32;
54 auto LenMVT = ST.hasAddr64() ? MVT::i64 : MVT::i32;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64SelectionDAGInfo.cpp | 68 Ptr = DAG.getTargetFrameIndex(FI, MVT::i64);
71 TagSrc = DAG.getRegister(AArch64::SP, MVT::i64);
126 const EVT ResTys[] = {MVT::i64, MVT::i64, MVT::Other};
131 Addr = DAG.getTargetFrameIndex(FI, MVT::i64);
136 SDValue Ops[] = {DAG.getTargetConstant(ObjSize, dl, MVT::i64), Addr, Chain};
|
| AArch64FastISel.cpp | 330 case MVT::i64: // fall-through
347 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i64 &&
371 if (VT > MVT::i64)
378 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
520 assert(VT == MVT::i64 && "Expected 64-bit pointers");
1052 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1056 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1061 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1064 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg()
[all...] |
| AArch64ISelDAGToDAG.cpp | 381 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
565 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
577 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
658 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
695 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, dl, MVT::i64);
842 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
862 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
877 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, dl, MVT::i64);
888 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
903 OffImm = CurDAG->getTargetConstant(0, dl, MVT::i64);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 121 clEnumValN(ICGPR_I64, "i64", "Only i64 comparisons in GPRs."),
128 "Only i64 comparisons with zext result."),
133 "Only i64 comparisons with sext result.")));
185 /// i64.
187 return CurDAG->getTargetConstant(Imm, dl, MVT::i64);
555 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
649 // Don't even go down this path for i64, since different logic will be
718 case MVT::i64: {
762 case MVT::i64:
[all...] |
| PPCFastISel.cpp | 442 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
469 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
490 case MVT::i64:
641 case MVT::i64:
841 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
922 case MVT::i64:
1009 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
1022 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
1033 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
1078 SrcVT != MVT::i32 && SrcVT != MVT::i64)
[all...] |
| PPCISelLowering.cpp | 164 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
203 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
208 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
217 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
231 isPPC64 ? MVT::i64 : MVT::i32);
234 isPPC64 ? MVT::i64 : MVT::i32);
238 isPPC64 ? MVT::i64 : MVT::i32);
241 isPPC64 ? MVT::i64 : MVT::i32);
245 isPPC64 ? MVT::i64 : MVT::i32);
248 isPPC64 ? MVT::i64 : MVT::i32)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/ |
| WebAssemblyTypeUtilities.cpp | 24 if (Type == "i64")
25 return wasm::ValType::I64;
51 .Case("i64", WebAssembly::BlockType::I64)
64 .Case("i64", MVT::i64)
67 .Case("i64", MVT::i64)
84 return "i64";
131 case MVT::i64
[all...] |
| /src/external/gpl2/xcvs/dist/lib/ |
| stdint_.h | 167 #define INT64_MAX 9223372036854775807i64
259 #define INT64_C(x) x##i64
272 #define INTMAX_C(x) x##i64
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 117 if (LocVT == MVT::i64 && Offset < 6*8)
165 LocVT = MVT::i64;
338 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
344 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
345 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
441 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
497 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
595 // All integer register arguments are promoted by the caller to i64.
670 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1071 // Full register, just bitconvert into i64
[all...] |
| /src/tests/include/ |
| t_inttypes.c | 43 int64_t i64 = 0; local
77 PRINT(PRId64, i64);
92 PRINT(PRIi64, i64);
168 SCAN(SCNd64, i64);
183 SCAN(SCNi64, i64);
|
| /src/sys/compat/netbsd32/ |
| netbsd32_drm.c | 617 info64to32(drm_agp_info32_t *i32, const struct drm_agp_info *i64)
619 i32->agp_version_major = i64->agp_version_major;
620 i32->agp_version_minor = i64->agp_version_minor;
621 i32->mode = i64->mode;
622 i32->aperture_base = i64->aperture_base;
623 i32->aperture_size = i64->aperture_size;
624 i32->memory_allowed = i64->memory_allowed;
625 i32->memory_used = i64->memory_used;
626 i32->id_vendor = i64->id_vendor;
627 i32->id_device = i64->id_device
634 struct drm_agp_info i64; local
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 748 MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32;
774 Mips::ZERO_64, MVT::i64);
810 DL, MVT::i64);
816 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
819 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
820 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
826 MVT::i64);
827 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
968 if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
989 if (ResTy != MVT::i32 && ResTy != MVT::i64)
[all...] |
| MipsISelLowering.cpp | 118 : MVT::i64;
366 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
367 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
368 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
369 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
370 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
371 setOperationAction(ISD::SELECT, MVT::i64, Custom);
372 setOperationAction(ISD::LOAD, MVT::i64, Custom);
373 setOperationAction(ISD::STORE, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 90 setOperationAction(ISD::LOAD, MVT::i64, Promote);
91 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
123 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
124 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
125 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
129 if (VT == MVT::i64)
210 setOperationAction(ISD::STORE, MVT::i64, Promote);
211 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
240 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
241 setTruncStoreAction(MVT::i64, MVT::i8, Expand)
[all...] |
| /src/external/bsd/zstd/dist/doc/educational_decoder/ |
| zstd_decompress.c | 68 typedef int64_t i64; typedef
145 i64 *const offset);
170 i64 *const offset);
174 i64 *const offset);
223 i64 *const offset);
228 i64 *const offset);
233 i64 *const offset);
1000 i64 *const offset,
1105 i64 bit_offset = (i64)(len * 8 - (size_t)padding)
[all...] |
| /src/bin/ps/ |
| ps.c | 666 int64_t i64; local
731 i64 = ka->p_rtime_sec * 1000000 + ka->p_rtime_usec;
732 i64 -= kb->p_rtime_sec * 1000000 + kb->p_rtime_usec;
734 i64 += ka->p_uctime_sec * 1000000
736 i64 -= kb->p_uctime_sec * 1000000
739 if (i64 != 0)
740 return i64 > 0 ? 1 : -1;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEISelLowering.cpp | 82 addRegisterClass(MVT::i64, &VE::I64RegClass);
140 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
158 for (MVT IntVT : {MVT::i32, MVT::i64}) {
182 // VE has 64 bits instruction which works as i64 BSWAP operation. This
187 // VE has only 64 bits instructions which work as i64 BITREVERSE/CTLZ/CTPOP
188 // operations. Use isel patterns for i64, promote for i32.
195 // VE has only 64 bits instructions which work as i64 AND/OR/XOR operations.
196 // Use isel patterns for i64, promote for i32.
205 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); // use i64
206 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVSubtarget.cpp | 67 XLenVT = MVT::i64;
|
| /src/external/bsd/libarchive/dist/libarchive/ |
| archive_private.h | 176 # define ARCHIVE_LITERAL_LL(x) x##i64
|
