HomeSort by: relevance | last modified time | path
    Searched refs:ipp (Results 1 - 25 of 25) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
ipp.h 1 /* $NetBSD: ipp.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
38 /* IPP RELATED */
73 struct input_pixel_processor *ipp,
78 struct input_pixel_processor *ipp,
85 struct input_pixel_processor *ipp);
87 /* setup ipp to expand/convert input to pixel processor internal format */
89 struct input_pixel_processor *ipp,
95 /* DCE function to setup IPP. TODO: see if we can consolidate to setup */
97 struct input_pixel_processor *ipp,
101 struct input_pixel_processor *ipp,
    [all...]
  /src/sys/fs/ntfs/
ntfs_ihash.c 120 struct nthashhead *ipp; local
123 ipp = &ntfs_nthashtbl[NTNOHASH(dev, inum)];
124 LIST_FOREACH(ip, ipp, i_hash) {
139 struct nthashhead *ipp; local
142 ipp = &ntfs_nthashtbl[NTNOHASH(ip->i_dev, ip->i_number)];
143 LIST_INSERT_HEAD(ipp, ip, i_hash);
ntfs_subr.c 393 ntfs_ntlookup(struct ntfsmount *ntmp, ino_t ino, struct ntnode **ipp)
400 if ((*ipp = ntfs_nthashlookup(ntmp->ntm_dev, ino)) != NULL) {
401 ntfs_ntget(*ipp);
403 (unsigned long long)ino, *ipp, (*ipp)->i_usecount));
412 if ((*ipp = ntfs_nthashlookup(ntmp->ntm_dev, ino)) != NULL) {
414 ntfs_ntget(*ipp);
417 (unsigned long long)ino, *ipp, (*ipp)->i_usecount));
436 *ipp = ip
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_ipp.c 49 struct input_pixel_processor *ipp,
53 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
75 struct input_pixel_processor *ipp,
78 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
145 static void dce_ipp_program_prescale(struct input_pixel_processor *ipp,
148 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
177 struct input_pixel_processor *ipp,
181 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
225 struct input_pixel_processor *ipp,
228 struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
    [all...]
dce_ipp.h 31 #include "ipp.h"
33 #define TO_DCE_IPP(ipp)\
34 container_of(ipp, struct dce_ipp, base)
238 void dce_ipp_destroy(struct input_pixel_processor **ipp);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_ipp.c 51 static void dcn10_ipp_destroy(struct input_pixel_processor **ipp)
53 kfree(TO_DCN10_IPP(*ipp));
54 *ipp = NULL;
dcn10_ipp.h 31 #include "ipp.h"
33 #define TO_DCN10_IPP(ipp)\
34 container_of(ipp, struct dcn10_ipp, base)
amdgpu_dcn10_resource.c 640 struct dcn10_ipp *ipp = local
643 if (!ipp) {
648 dcn10_ipp_construct(ipp, ctx, inst,
650 return &ipp->base;
1155 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
1492 /* mem input -> ipp -> dpp -> opp -> TG */
  /src/sys/compat/netbsd32/
netbsd32_conv.h 563 struct ipc_perm *ipp)
566 memset(ipp, 0, sizeof(*ipp));
567 ipp->cuid = ip32p->cuid;
568 ipp->cgid = ip32p->cgid;
569 ipp->uid = ip32p->uid;
570 ipp->gid = ip32p->gid;
571 ipp->mode = ip32p->mode;
572 ipp->_seq = ip32p->_seq;
573 ipp->_key = (key_t)ip32p->_key
    [all...]
  /src/sys/arch/sparc/dev/
sbus.c 525 struct openprom_intr **ipp, int *np)
544 *ipp = ip;
551 *ipp = NULL;
553 np, ipp);
557 (*ipp)[n].oi_pri &= 0xf;
558 (*ipp)[n].oi_pri |= SBUS_INTR_COMPAT;
  /src/sys/dev/acpi/
apei_erst.c 376 void *cookie, uint32_t *ipp, uint32_t maxip)
492 if (*ipp < maxip)
493 (*ipp)++;
498 *ipp = maxip;
500 *ipp = Value;
apei_einj.c 399 void *cookie, uint32_t *ipp, uint32_t maxip)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 51 #include "ipp.h"
281 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; local
286 if (ipp == NULL)
293 ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
298 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
302 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB)
2679 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; local
    [all...]
amdgpu_dce110_resource.c 640 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); local
642 if (!ipp) {
647 dce_ipp_construct(ipp, ctx, inst,
649 return &ipp->base;
1115 /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/
amdgpu_dce100_resource.c 594 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); local
596 if (!ipp) {
601 dce_ipp_construct(ipp, ctx, inst,
603 return &ipp->base;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_resource.c 726 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); local
728 if (!ipp) {
733 dce_ipp_construct(ipp, ctx, inst,
735 return &ipp->base;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 251 struct input_pixel_processor *ipp; member in struct:plane_resource
  /src/sys/arch/sparc64/dev/
sbus.c 433 sbus_get_intr(struct sbus_softc *sc, int node, struct openprom_intr **ipp,
491 *ipp = ip;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_resource.c 641 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); local
643 if (!ipp) {
648 dce_ipp_construct(ipp, ctx, inst,
650 return &ipp->base;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
amdgpu_dce80_resource.c 769 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); local
771 if (!ipp) {
776 dce_ipp_construct(ipp, ctx, inst,
778 return &ipp->base;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_resource.c 678 struct dcn10_ipp *ipp = local
681 if (!ipp) {
686 dcn20_ipp_construct(ipp, ctx, inst,
688 return &ipp->base;
1798 /* mem input -> ipp -> dpp -> opp -> TG */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 997 struct dcn10_ipp *ipp = local
1000 if (!ipp) {
1005 dcn20_ipp_construct(ipp, ctx, inst,
1007 return &ipp->base;
1739 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1814 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
3003 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3673 /* mem input -> ipp -> dpp -> opp -> TG */
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_stream.c 39 #include "ipp.h"
352 (!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
amdgpu_dc_resource.c 1246 split_pipe->plane_res.ipp = pool->ipps[i];
1649 pipe_ctx->plane_res.ipp = pool->ipps[i];
1920 pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 527 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];

Completed in 38 milliseconds