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    Searched refs:isVShiftRImm (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerLowering.cpp 473 /// isVShiftRImm - Check if this is a valid vector for the immediate
476 static bool isVShiftRImm(Register Reg, MachineRegisterInfo &MRI, LLT Ty,
496 return isVShiftRImm(MI.getOperand(2).getReg(), MRI, Ty, Imm);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 6281 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6287 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6328 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
15910 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
15919 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
15942 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
16006 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
16172 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 10321 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
10324 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
10389 if (isVShiftRImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize) {

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