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Searched refs:ixCG_CLKPIN_CNTL (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_fiji_baco.c	`105 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },`
amdgpu_polaris_baco.c	`108 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },`
amdgpu_tonga_baco.c	`113 { CMD_WRITE, mmGCK_SMC_IND_INDEX, 0, 0, 0, ixCG_CLKPIN_CNTL },`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik.c	`856 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) 1770 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); 1773 WREG32_SMC(ixCG_CLKPIN_CNTL, data);`
amdgpu_vi.c	`346 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL);`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_d.h	`58 #define ixCG_CLKPIN_CNTL 0xc05001a0`
smu_7_0_1_d.h	`59 #define ixCG_CLKPIN_CNTL 0xc05001a0`
smu_7_1_0_d.h	`58 #define ixCG_CLKPIN_CNTL 0xc05001a0`
smu_7_1_1_d.h	`58 #define ixCG_CLKPIN_CNTL 0xc05001a0`
smu_7_1_2_d.h	`59 #define ixCG_CLKPIN_CNTL 0xc05001a0`
smu_7_1_3_d.h	`62 #define ixCG_CLKPIN_CNTL 0xc05001a0`

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