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    Searched refs:link_rate (Results 1 - 25 of 30) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link_dp.c 170 rate = (uint8_t) (lt_settings->link_settings.link_rate);
178 lt_settings->link_settings.link_rate,
506 max_lt_setting->link_settings.link_rate =
507 link_training_setting->link_settings.link_rate;
610 request_settings.link_settings.link_rate =
611 link_training_setting->link_settings.link_rate;
1115 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
1116 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
1118 lt_settings->link_settings.link_rate = link_setting->link_rate
1294 const char *link_rate = "Unknown"; local in function:print_status_message
3528 enum dc_link_rate link_rate; local in function:linkRateInKHzToLinkRateMultiplier
3567 enum dc_link_rate link_rate = LINK_RATE_UNKNOWN; local in function:detect_edp_sink_caps
    [all...]
amdgpu_dc_link.c 572 link->cur_link_settings.link_rate =
582 link->cur_link_settings.link_rate = link_bw_set;
1519 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1525 if (link_settings.link_rate == LINK_RATE_LOW)
3317 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3336 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3376 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3414 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dp_link_training.c 147 intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
262 } else if (intel_dp->link_rate == 810000) {
277 } else if (intel_dp->link_rate >= 540000) {
373 intel_dp->link_rate, intel_dp->lane_count);
380 intel_dp->link_rate, intel_dp->lane_count);
382 intel_dp->link_rate,
intel_dp.h 53 int link_rate, u8 lane_count,
56 int link_rate, u8 lane_count);
intel_dp.c 426 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
434 if (link_rate == 0 ||
435 link_rate > intel_dp->max_link_rate)
446 int link_rate,
454 max_rate = intel_dp_max_data_rate(link_rate, lane_count);
462 int link_rate, u8 lane_count)
468 link_rate);
2499 int link_rate, u8 lane_count,
2503 intel_dp->link_rate = link_rate;
    [all...]
intel_ddi.c 2381 intel_dp->link_rate, &n_entries);
2387 intel_dp->link_rate, &n_entries);
2515 rate = intel_dp->link_rate;
2641 rate = intel_dp->link_rate;
2921 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2924 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
intel_display_types.h 1227 int link_rate; member in struct:intel_dp
  /src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
amdgpu_dm_debugfs.c 42 * get/ set DP configuration: lane_count, link_rate, spread_spectrum
66 * echo <lane_count> <link_rate> > link_settings
106 link->cur_link_settings.link_rate,
113 link->verified_link_cap.link_rate,
120 link->reported_link_cap.link_rate,
127 link->preferred_link_setting.link_rate,
161 /* 0: lane_count; 1: link_rate */
231 /* save user force lane_count, link_rate to preferred settings
236 prefer_link_settings.link_rate = param[1];
264 * from lane_count, link_rate to figure which DP-x is for display to be worke
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dce110/
amdgpu_dce110_clk_mgr.c 162 cfg->link_settings.link_rate =
163 stream->link->cur_link_settings.link_rate;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/
dmub_cmd.h 240 uint8_t link_rate; member in struct:dmub_cmd_psr_copy_settings_data
  /src/sys/external/bsd/drm2/dist/drm/amd/display/include/
bios_parser_types.h 120 enum dc_link_rate link_rate; member in struct:bp_external_encoder_control
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_link_encoder.c 223 switch (link_settings->link_rate) {
238 __func__, link_settings->link_rate);
amdgpu_dcn20_stream_encoder.c 457 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
474 param->link_settings.link_rate
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
amdgpu_dcn21_link_encoder.c 189 switch (link_settings->link_rate) {
204 __func__, link_settings->link_rate);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
amdgpu_dce_link_encoder.c 1014 cntl.pixel_clock = link_settings->link_rate
1053 cntl.pixel_clock = link_settings->link_rate
1132 cntl.pixel_clock = link_settings->link_settings.link_rate *
1144 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
dce_dmcu.h 245 unsigned int link_rate:4; /*[19:16]*/ member in struct:dce_dmcu_psr_config_data_reg3::__anonbf059aaf0308
dmub_psr.c 176 copy_settings_data->link_rate = psr_context->frame_delay & 0xF;
amdgpu_dce_stream_encoder.c 980 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
992 param->link_settings.link_rate
dce_clk_mgr.c 534 cfg->link_settings.link_rate =
535 stream->link->cur_link_settings.link_rate;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_link_encoder.c 976 cntl.pixel_clock = link_settings->link_rate
1015 cntl.pixel_clock = link_settings->link_rate
1098 cntl.pixel_clock = link_settings->link_settings.link_rate *
1110 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
amdgpu_dcn10_stream_encoder.c 937 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
954 param->link_settings.link_rate
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc_dp_types.h 104 enum dc_link_rate link_rate; member in struct:dc_link_settings
  /src/sys/external/bsd/drm2/dist/drm/
drm_dp_helper.c 185 u8 drm_dp_link_rate_to_bw_code(int link_rate)
187 /* Spec says link_bw = link_rate / 0.27Gbps */
188 return link_rate / 27000;
194 /* Spec says link_rate = link_bw * 0.27Gbps */
  /src/sys/external/bsd/drm2/dist/include/drm/
drm_dp_helper.h 1152 u8 drm_dp_link_rate_to_bw_code(int link_rate);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_hw_sequencer.c 1060 params.link_settings.link_rate = link_settings->link_rate;

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