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    Searched refs:max_supported_dppclk_khz (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/
amdgpu_rv1_clk_mgr.c 51 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz;
127 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn20/
amdgpu_dcn20_clk_mgr.c 394 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dc.h 294 int max_supported_dppclk_khz; member in struct:dc_clocks
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 1154 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1158 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1162 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
1166 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz =
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc.c 2696 info->maxSupportedDppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 452 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
457 dc->current_state->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz,
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_resource.c 2853 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;

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