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    Searched refs:mmCOMPUTE_PGM_RSRC1 (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_6_0_d.h 335 #define mmCOMPUTE_PGM_RSRC1 0x2E12
gfx_7_0_d.h 1206 #define mmCOMPUTE_PGM_RSRC1 0x2e12
gfx_7_2_d.h 1219 #define mmCOMPUTE_PGM_RSRC1 0x2e12
gfx_8_0_d.h 1301 #define mmCOMPUTE_PGM_RSRC1 0x2e12
gfx_8_1_d.h 1304 #define mmCOMPUTE_PGM_RSRC1 0x2e12
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v8_0.c 1437 mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */
1458 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
1479 mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */
amdgpu_gfx_v9_0.c 4070 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f },
4087 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
4104 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h 2211 #define mmCOMPUTE_PGM_RSRC1 0x0e12
gc_9_1_offset.h 2496 #define mmCOMPUTE_PGM_RSRC1 0x0e12
gc_9_2_1_offset.h 2430 #define mmCOMPUTE_PGM_RSRC1 0x0e12
gc_10_1_0_offset.h 4570 #define mmCOMPUTE_PGM_RSRC1 0x1bb2
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