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Searched refs:mmCP_CPC_IC_BASE_LO (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu8_smumgr.c	`215 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`2342 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2942 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &`
amdgpu_gfx_v9_0.c	`3285 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_8_0_d.h	`348 #define mmCP_CPC_IC_BASE_LO 0x30b9`
gfx_8_1_d.h	`348 #define mmCP_CPC_IC_BASE_LO 0x30b9`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
polaris10_pwrvirus.h	`60 { 0x540ff000, mmCP_CPC_IC_BASE_LO },`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2600 #define mmCP_CPC_IC_BASE_LO 0x10b9`
gc_9_1_offset.h	`2870 #define mmCP_CPC_IC_BASE_LO 0x10b9`
gc_9_2_1_offset.h	`2804 #define mmCP_CPC_IC_BASE_LO 0x10b9`
gc_10_1_0_offset.h	`[all...]`

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