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Searched refs:mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gca/
gfx_7_0_d.h	`581 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251`
gfx_7_2_d.h	`594 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251`
gfx_8_0_d.h	`644 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251`
gfx_8_1_d.h	`644 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v10_0.c	`3420 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,`
amdgpu_gfx_v9_0.c	`3527 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_0_offset.h	`2840 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251`
gc_9_1_offset.h	`3068 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251`
gc_9_2_1_offset.h	`3024 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1251`
gc_10_1_0_offset.h	`5306 #define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5 [all...]`

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