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    Searched refs:mmSPI_WAVE_LIMIT_CNTL_BASE_IDX (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_9_2_1_offset.h	5329 #define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX 1
gc_10_1_0_offset.h	2597 #define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX 0     [all...]

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