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    Searched refs:mmUVD_CXW_WR_INT_ID (Results 1 - 2 of 2) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_2_0_0_offset.h	514 #define mmUVD_CXW_WR_INT_ID 0x01ee
vcn_2_5_offset.h	611 #define mmUVD_CXW_WR_INT_ID 0x00ca

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