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Searched refs:mmVCE_UENC_DMA_DCLK_CTRL (Results 1 - 5 of 5) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h	`56 #define mmVCE_UENC_DMA_DCLK_CTRL 0x8250`
vce_2_0_d.h	`51 #define mmVCE_UENC_DMA_DCLK_CTRL 0x8390`
vce_3_0_d.h	`56 #define mmVCE_UENC_DMA_DCLK_CTRL 0x8390`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v3_0.c	`206 data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL); 211 WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data); 230 data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL); 235 WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);`
amdgpu_vce_v4_0.c	`847 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); 852 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data); 871 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL)); 876 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);`

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