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    Searched refs:mmVCE_VCPU_CACHE_OFFSET0 (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_1_0_d.h 58 #define mmVCE_VCPU_CACHE_OFFSET0 0x8009
vce_2_0_d.h 31 #define mmVCE_VCPU_CACHE_OFFSET0 0x8009
vce_3_0_d.h 31 #define mmVCE_VCPU_CACHE_OFFSET0 0x8009
vce_4_0_offset.h 34 #define mmVCE_VCPU_CACHE_OFFSET0 0x0a09
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v4_0.c 265 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
273 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0),
634 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);
640 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000);
amdgpu_vce_v2_0.c 192 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
amdgpu_vce_v3_0.c 553 WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);

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