| /src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| intel_engine.h | 58 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
68 lower_reg__((engine__)->mmio_base), \
69 upper_reg__((engine__)->mmio_base))
72 __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
75 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
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| intel_rc6.c | 74 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
139 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
203 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
230 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
355 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
382 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
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| intel_engine_cs.c | 312 engine->mmio_base = __engine_mmio_base(gt->i915, info->mmio_bases);
882 const u32 base = engine->mmio_base;
978 u32 mmio_base = engine->mmio_base; local in function:intel_engine_get_instdone
987 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1005 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1022 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1039 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1553 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
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| intel_ring_submission.c | 573 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
575 hwsp = RING_HWS_PGA(engine->mmio_base);
596 RING_INSTPM(engine->mmio_base),
619 RING_MI_MODE(engine->mmio_base),
715 RING_CTL(engine->mmio_base),
752 const u32 base = engine->mmio_base;
1384 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
1388 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
1393 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
1398 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
[all...] |
| intel_workarounds.c | 1231 whitelist_reg_ext(w, _MMIO(0x2000 + engine->mmio_base),
1234 whitelist_reg_ext(w, _MMIO(0x2014 + engine->mmio_base),
1237 whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base),
1305 const u32 base = engine->mmio_base;
1477 RING_SEMA_WAIT_POLL(engine->mmio_base),
|
| intel_engine_types.h | 297 u32 mmio_base; member in struct:intel_engine_cs
|
| selftest_lrc.c | 28 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
3776 i915_mmio_reg_offset(RING_START(engine->mmio_base)),
3781 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)),
3786 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)),
3791 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)),
3796 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)),
3801 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)),
3877 *cs++ = i915_mmio_reg_offset(RING_START(engine->mmio_base));
3884 *cs++ = i915_mmio_reg_offset(RING_TAIL(engine->mmio_base));
|
| intel_reset.c | 498 const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
535 RING_RESET_CTL(engine->mmio_base),
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| selftest_workarounds.c | 105 const u32 base = engine->mmio_base;
189 RING_NOPID(engine->mmio_base);
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| intel_lrc.c | 558 const u32 base = engine->mmio_base;
4393 u32 base = engine->mmio_base;
|
| /src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| intel_uncore.c | 197 i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
198 u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
|
| /src/sys/external/bsd/drm/dist/shared-core/ |
| savage_bci.c | 563 unsigned long mmio_base, fb_base, fb_size, aperture_base; local in function:savage_driver_firstopen
578 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
606 mmio_base = drm_get_resource_start(dev, 0);
626 mmio_base = drm_get_resource_start(dev, 0);
637 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
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| mga_dma.c | 411 dev_priv->mmio_base = drm_get_resource_start(dev, 1);
720 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
|
| mga_drv.h | 116 u32 mmio_base; /**< Bus address of base of MMIO. */ member in struct:drm_mga_private
|
| /src/sys/external/bsd/drm2/dist/drm/savage/ |
| savage_bci.c | 580 unsigned long mmio_base, fb_base, fb_size, aperture_base; local in function:savage_driver_firstopen
592 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
614 mmio_base = pci_resource_start(dev->pdev, 0);
633 mmio_base = pci_resource_start(dev->pdev, 0);
642 ret = drm_legacy_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE,
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| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| scheduler.c | 221 u32 ring_base = dev_priv->engine[ring_id]->mmio_base;
579 ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
819 ring_base = dev_priv->engine[workload->ring_id]->mmio_base;
|
| execlist.c | 48 (gvt->dev_priv->engine[ring_id]->mmio_base + (offset))
|
| handlers.c | 165 if (engine->mmio_base == offset)
533 ring_base = dev_priv->engine[ring_id]->mmio_base;
1674 ring_base = dev_priv->engine[ring_id]->mmio_base;
|
| /src/sys/external/bsd/drm2/dist/drm/mga/ |
| mga_dma.c | 429 dev_priv->mmio_base = pci_resource_start(dev->pdev, 1);
734 err = drm_legacy_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
|
| mga_drv.h | 133 resource_size_t mmio_base; /**< Bus address of base of MMIO. */ member in struct:drm_mga_private
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/ |
| nouveau_nvkm_engine_device_base.c | 2972 u64 mmio_base, mmio_size; local in function:nvkm_device_ctor
3008 mmio_base = device->func->resource_addr(device, 0);
3019 ret = -bus_space_map(mmiot, mmio_base, 0x102000, 0, &mmioh);
3037 map = ioremap(mmio_base, 0x102000);
3236 ret = -bus_space_map(mmiot, mmio_base, mmio_size,
3244 device->mmioaddr = mmio_base;
3247 device->pri = ioremap(mmio_base, mmio_size);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_gpu_error.c | 1182 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1185 mmio = RING_HWS_PGA(engine->mmio_base);
1205 u32 base = engine->mmio_base;
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| i915_perf.c | 1766 const u32 base = stream->engine->mmio_base;
2353 RING_CONTEXT_CONTROL(ce->engine->mmio_base),
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| i915_reg.h | 409 #define GEN11_VCS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x88C)
411 #define GEN11_VCS_SFC_LOCK_STATUS(engine) _MMIO((engine)->mmio_base + 0x890)
415 #define GEN11_VECS_SFC_FORCED_LOCK(engine) _MMIO((engine)->mmio_base + 0x201C)
417 #define GEN11_VECS_SFC_LOCK_ACK(engine) _MMIO((engine)->mmio_base + 0x2018)
419 #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gem/ |
| i915_gem_context.c | 1113 u32 base = engine->mmio_base;
|
