| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_nbio.c | 41 if (!adev->nbio.ras_if) {
42 adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
43 if (!adev->nbio.ras_if)
45 adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;
46 adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
47 adev->nbio.ras_if->sub_block_index = 0;
48 strcpy(adev->nbio.ras_if->name, "pcie_bif");
50 ih_info.head = fs_info.head = *adev->nbio.ras_if;
51 r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,
56 if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block))
[all...] |
| amdgpu_soc15.c | 52 #include "nbio/nbio_7_0_default.h"
53 #include "nbio/nbio_7_0_offset.h"
54 #include "nbio/nbio_7_0_sh_mask.h"
55 #include "nbio/nbio_7_0_smn.h"
106 address = adev->nbio.funcs->get_pcie_index_offset(adev);
107 data = adev->nbio.funcs->get_pcie_data_offset(adev);
121 address = adev->nbio.funcs->get_pcie_index_offset(adev);
122 data = adev->nbio.funcs->get_pcie_data_offset(adev);
136 address = adev->nbio.funcs->get_pcie_index_offset(adev);
137 data = adev->nbio.funcs->get_pcie_data_offset(adev)
[all...] |
| amdgpu_nv.c | 77 address = adev->nbio.funcs->get_pcie_index_offset(adev);
78 data = adev->nbio.funcs->get_pcie_data_offset(adev);
92 address = adev->nbio.funcs->get_pcie_index_offset(adev);
93 data = adev->nbio.funcs->get_pcie_data_offset(adev);
133 return adev->nbio.funcs->get_memsize(adev);
313 u32 memsize = adev->nbio.funcs->get_memsize(adev);
417 adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
418 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
472 adev->nbio.funcs = &nbio_v2_3_funcs;
473 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg
[all...] |
| amdgpu_nbio_v7_4.c | 33 #include "nbio/nbio_7_4_offset.h"
34 #include "nbio/nbio_7_4_sh_mask.h"
35 #include "nbio/nbio_7_4_0_smn.h"
36 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
42 * These are nbio v7_4_1 registers mask. Temporarily define these here since
43 * nbio v7_4_1 header is incomplete.
65 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
67 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
73 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
84 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN
[all...] |
| amdgpu_df_v3_6.c | 114 address = adev->nbio.funcs->get_pcie_index_offset(adev);
115 data = adev->nbio.funcs->get_pcie_data_offset(adev);
137 address = adev->nbio.funcs->get_pcie_index_offset(adev);
138 data = adev->nbio.funcs->get_pcie_data_offset(adev);
165 address = adev->nbio.funcs->get_pcie_index_offset(adev);
166 data = adev->nbio.funcs->get_pcie_data_offset(adev);
187 address = adev->nbio.funcs->get_pcie_index_offset(adev);
188 data = adev->nbio.funcs->get_pcie_data_offset(adev);
206 address = adev->nbio.funcs->get_pcie_index_offset(adev);
207 data = adev->nbio.funcs->get_pcie_data_offset(adev)
[all...] |
| amdgpu_irq.c | 172 if (adev->nbio.funcs &&
173 adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
174 adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
176 if (adev->nbio.funcs &&
177 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
178 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
|
| amdgpu_ras.c | 39 #include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
731 if (adev->nbio.funcs->query_ras_error_count)
732 adev->nbio.funcs->query_ras_error_count(adev, &err_data);
1793 if (adev->nbio.funcs->init_ras_controller_interrupt) {
1794 r = adev->nbio.funcs->init_ras_controller_interrupt(adev);
1799 if (adev->nbio.funcs->init_ras_err_event_athub_interrupt) {
1800 r = adev->nbio.funcs->init_ras_err_event_athub_interrupt(adev);
|
| amdgpu_navi10_ih.c | 124 adev->nbio.funcs->ih_control(adev);
169 adev->nbio.funcs->ih_doorbell_range(adev, ih->use_doorbell,
|
| amdgpu_gmc_v10_0.c | 351 adev->nbio.funcs->hdp_flush(adev, NULL);
694 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
940 adev->nbio.funcs->hdp_flush(adev, NULL);
|
| amdgpu_jpeg_v2_5.c | 175 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
|
| amdgpu_sdma_v5_0.c | 423 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
433 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
434 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
700 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
|
| amdgpu_jpeg_v2_0.c | 157 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
|
| amdgpu_vega10_ih.c | 234 adev->nbio.funcs->ih_control(adev);
|
| amdgpu_gmc_v9_0.c | 965 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1369 adev->nbio.funcs->hdp_flush(adev, NULL);
|
| amdgpu_gfx_v10_0.c | 2473 adev->nbio.funcs->hdp_flush(adev, NULL);
2543 adev->nbio.funcs->hdp_flush(adev, NULL);
2612 adev->nbio.funcs->hdp_flush(adev, NULL);
2934 adev->nbio.funcs->hdp_flush(adev, NULL);
4383 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4403 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4404 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
|
| amdgpu_sdma_v4_0.c | 857 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
862 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
863 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
|
| amdgpu_psp_v11_0.c | 43 #include "nbio/nbio_7_4_offset.h"
1069 adev->nbio.funcs->hdp_flush(adev, NULL);
|
| amdgpu.h | 894 /* nbio */
895 struct amdgpu_nbio nbio; member in struct:amdgpu_device
|
| amdgpu_vcn_v2_0.c | 210 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
|
| amdgpu_vcn_v2_5.c | 283 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
|
| amdgpu_device.c | 4582 adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
4601 adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
|
| amdgpu_gfx_v9_0.c | 4885 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
4905 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
4906 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
|
