| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/ |
| nouveau_nvkm_engine_gr_nv25.c | 47 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
48 nvkm_wo32(chan->inst, 0x035c, 0xffff0000);
49 nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000);
50 nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000);
51 nvkm_wo32(chan->inst, 0x049c, 0x00000101);
52 nvkm_wo32(chan->inst, 0x04b0, 0x00000111);
53 nvkm_wo32(chan->inst, 0x04c8, 0x00000080);
54 nvkm_wo32(chan->inst, 0x04cc, 0xffff0000);
55 nvkm_wo32(chan->inst, 0x04d0, 0x00000001);
56 nvkm_wo32(chan->inst, 0x04e4, 0x44400000)
[all...] |
| nouveau_nvkm_engine_gr_nv34.c | 47 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
48 nvkm_wo32(chan->inst, 0x040c, 0x01000101);
49 nvkm_wo32(chan->inst, 0x0420, 0x00000111);
50 nvkm_wo32(chan->inst, 0x0424, 0x00000060);
51 nvkm_wo32(chan->inst, 0x0440, 0x00000080);
52 nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
53 nvkm_wo32(chan->inst, 0x0448, 0x00000001);
54 nvkm_wo32(chan->inst, 0x045c, 0x44400000);
55 nvkm_wo32(chan->inst, 0x0480, 0xffff0000);
57 nvkm_wo32(chan->inst, i, 0x0fff0000)
[all...] |
| nouveau_nvkm_engine_gr_nv35.c | 47 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
48 nvkm_wo32(chan->inst, 0x040c, 0x00000101);
49 nvkm_wo32(chan->inst, 0x0420, 0x00000111);
50 nvkm_wo32(chan->inst, 0x0424, 0x00000060);
51 nvkm_wo32(chan->inst, 0x0440, 0x00000080);
52 nvkm_wo32(chan->inst, 0x0444, 0xffff0000);
53 nvkm_wo32(chan->inst, 0x0448, 0x00000001);
54 nvkm_wo32(chan->inst, 0x045c, 0x44400000);
55 nvkm_wo32(chan->inst, 0x0488, 0xffff0000);
57 nvkm_wo32(chan->inst, i, 0x0fff0000)
[all...] |
| nouveau_nvkm_engine_gr_nv2a.c | 47 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
48 nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
49 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
50 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
51 nvkm_wo32(chan->inst, 0x047c, 0x00000101);
52 nvkm_wo32(chan->inst, 0x0490, 0x00000111);
53 nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
55 nvkm_wo32(chan->inst, i, 0x00030303);
57 nvkm_wo32(chan->inst, i, 0x00080000);
59 nvkm_wo32(chan->inst, i, 0x01012000)
[all...] |
| nouveau_nvkm_engine_gr_nv30.c | 48 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24));
49 nvkm_wo32(chan->inst, 0x0410, 0x00000101);
50 nvkm_wo32(chan->inst, 0x0424, 0x00000111);
51 nvkm_wo32(chan->inst, 0x0428, 0x00000060);
52 nvkm_wo32(chan->inst, 0x0444, 0x00000080);
53 nvkm_wo32(chan->inst, 0x0448, 0xffff0000);
54 nvkm_wo32(chan->inst, 0x044c, 0x00000001);
55 nvkm_wo32(chan->inst, 0x0460, 0x44400000);
56 nvkm_wo32(chan->inst, 0x048c, 0xffff0000);
58 nvkm_wo32(chan->inst, i, 0x0fff0000)
[all...] |
| nouveau_nvkm_engine_gr_nv20.c | 29 nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4);
59 nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000);
101 nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24));
102 nvkm_wo32(chan->inst, 0x033c, 0xffff0000);
103 nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000);
104 nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000);
105 nvkm_wo32(chan->inst, 0x047c, 0x00000101);
106 nvkm_wo32(chan->inst, 0x0490, 0x00000111);
107 nvkm_wo32(chan->inst, 0x04a8, 0x44400000);
109 nvkm_wo32(chan->inst, i, 0x00030303)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/fifo/ |
| nouveau_nvkm_engine_fifo_dmag84.c | 73 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
74 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
75 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
76 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
77 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
80 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
81 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
82 nvkm_wo32(chan->ramfc, 0x78, 0x00000000)
[all...] |
| nouveau_nvkm_engine_fifo_dmanv50.c | 73 nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));
74 nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));
75 nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));
76 nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));
77 nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);
78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
80 nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);
81 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
82 nvkm_wo32(chan->ramfc, 0x78, 0x00000000)
[all...] |
| nouveau_nvkm_engine_fifo_gpfifog84.c | 77 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);
78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
80 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset));
81 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
82 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
83 nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
84 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
85 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
88 nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10)
[all...] |
| nouveau_nvkm_engine_fifo_gpfifonv50.c | 77 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078);
78 nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);
79 nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);
80 nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset));
81 nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
82 nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);
83 nvkm_wo32(chan->ramfc, 0x78, 0x00000000);
84 nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);
85 nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
|
| nouveau_nvkm_engine_fifo_gpfifogv100.c | 87 nvkm_wo32(inst, 0x0210, 0x00000000);
88 nvkm_wo32(inst, 0x0214, 0x00000000);
107 nvkm_wo32(inst, 0x210, lower_32_bits(addr) | 0x00000004);
108 nvkm_wo32(inst, 0x214, upper_32_bits(addr));
188 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
208 nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem));
209 nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem));
210 nvkm_wo32(chan->base.inst, 0x010, 0x0000face);
211 nvkm_wo32(chan->base.inst, 0x030, 0x7ffff902);
212 nvkm_wo32(chan->base.inst, 0x048, lower_32_bits(ioffset))
[all...] |
| nouveau_nvkm_engine_fifo_gpfifogk104.c | 117 nvkm_wo32(inst, (offset & 0xffff) + 0x00, 0x00000000);
118 nvkm_wo32(inst, (offset & 0xffff) + 0x04, 0x00000000);
120 nvkm_wo32(inst, offset + 0x00, 0x00000000);
121 nvkm_wo32(inst, offset + 0x04, 0x00000000);
142 nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo);
143 nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi);
145 nvkm_wo32(inst, offset + 0x00, datalo);
146 nvkm_wo32(inst, offset + 0x04, datahi);
308 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
314 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem))
[all...] |
| nouveau_nvkm_engine_fifo_gk110.c | 41 nvkm_wo32(memory, offset + 0, (cgrp->chan_nr << 26) | (128 << 18) |
43 nvkm_wo32(memory, offset + 4, 0x00000000);
|
| nouveau_nvkm_engine_fifo_channv50.c | 94 nvkm_wo32(chan->eng, offset + 0x00, 0x00000000);
95 nvkm_wo32(chan->eng, offset + 0x04, 0x00000000);
96 nvkm_wo32(chan->eng, offset + 0x08, 0x00000000);
97 nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000);
98 nvkm_wo32(chan->eng, offset + 0x10, 0x00000000);
99 nvkm_wo32(chan->eng, offset + 0x14, 0x00000000);
122 nvkm_wo32(chan->eng, offset + 0x00, 0x00190000);
123 nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit));
124 nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start));
125 nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24
[all...] |
| nouveau_nvkm_engine_fifo_gpfifogf100.c | 102 nvkm_wo32(inst, offset + 0x00, 0x00000000);
103 nvkm_wo32(inst, offset + 0x04, 0x00000000);
121 nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4);
122 nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr));
273 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
279 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
280 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
281 nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
282 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
283 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset))
[all...] |
| nouveau_nvkm_engine_fifo_chang84.c | 126 nvkm_wo32(chan->eng, offset + 0x00, 0x00000000);
127 nvkm_wo32(chan->eng, offset + 0x04, 0x00000000);
128 nvkm_wo32(chan->eng, offset + 0x08, 0x00000000);
129 nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000);
130 nvkm_wo32(chan->eng, offset + 0x10, 0x00000000);
131 nvkm_wo32(chan->eng, offset + 0x14, 0x00000000);
153 nvkm_wo32(chan->eng, offset + 0x00, 0x00190000);
154 nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit));
155 nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start));
156 nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24
[all...] |
| nouveau_nvkm_engine_fifo_dmanv10.c | 82 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
83 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
84 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4);
85 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14,
|
| nouveau_nvkm_engine_fifo_dmanv17.c | 83 nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
84 nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
85 nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4);
86 nvkm_wo32(imem->ramfc, chan->ramfc + 0x14,
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/mmu/ |
| nouveau_nvkm_subdev_mmu_vmmgv100.c | 48 nvkm_wo32(inst, 0x21c, 0x00000000);
52 nvkm_wo32(inst, 0x2a4 + (i * 0x10), data[1]);
53 nvkm_wo32(inst, 0x2a0 + (i * 0x10), data[0]);
55 nvkm_wo32(inst, 0x2a4 + (i * 0x10), 0x00000001);
56 nvkm_wo32(inst, 0x2a0 + (i * 0x10), 0x00000001);
58 nvkm_wo32(inst, 0x2a8 + (i * 0x10), 0x00000000);
61 nvkm_wo32(inst, 0x298, lower_32_bits(mask));
62 nvkm_wo32(inst, 0x29c, upper_32_bits(mask));
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/dma/ |
| nouveau_nvkm_engine_dma_usergf119.c | 55 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
56 nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8);
57 nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8);
58 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
59 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
60 nvkm_wo32(*pgpuobj, 0x14, 0x00000000);
|
| nouveau_nvkm_engine_dma_usergv100.c | 55 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
56 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(start));
57 nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start));
58 nvkm_wo32(*pgpuobj, 0x0c, lower_32_bits(limit));
59 nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit));
|
| nouveau_nvkm_engine_dma_usergf100.c | 56 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
57 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
58 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
59 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
61 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
62 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
|
| nouveau_nvkm_engine_dma_usernv50.c | 56 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
57 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
58 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
59 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
61 nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
62 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bar/ |
| nouveau_nvkm_subdev_bar_nv50.c | 161 nvkm_wo32(bar->bar2, 0x00, 0x7fc00000);
162 nvkm_wo32(bar->bar2, 0x04, lower_32_bits(limit));
163 nvkm_wo32(bar->bar2, 0x08, lower_32_bits(start));
164 nvkm_wo32(bar->bar2, 0x0c, upper_32_bits(limit) << 24 |
166 nvkm_wo32(bar->bar2, 0x10, 0x00000000);
167 nvkm_wo32(bar->bar2, 0x14, 0x00000000);
197 nvkm_wo32(bar->bar1, 0x00, 0x7fc00000);
198 nvkm_wo32(bar->bar1, 0x04, lower_32_bits(limit));
199 nvkm_wo32(bar->bar1, 0x08, lower_32_bits(start));
200 nvkm_wo32(bar->bar1, 0x0c, upper_32_bits(limit) << 24
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/cipher/ |
| nouveau_nvkm_engine_cipher_g84.c | 46 nvkm_wo32(*pgpuobj, 0x00, object->oclass);
47 nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
48 nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
49 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
|
