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    Searched refs:pipe_dlg_param (Results 1 - 5 of 5) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
amdgpu_dcn20_hwseq.c 656 pipe_ctx->pipe_dlg_param.vready_offset,
657 pipe_ctx->pipe_dlg_param.vstartup_start,
658 pipe_ctx->pipe_dlg_param.vupdate_offset,
659 pipe_ctx->pipe_dlg_param.vupdate_width,
1214 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1215 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1216 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offse
    [all...]
amdgpu_dcn20_resource.c 2847 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
amdgpu_dcn_calcs.c 436 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
437 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
438 input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
439 input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
1183 pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
1184 pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx];
1185 pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx];
1186 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
1188 pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
1189 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
core_types.h 300 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; member in struct:pipe_ctx
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_hw_sequencer.c 811 pipe_ctx->pipe_dlg_param.vready_offset,
812 pipe_ctx->pipe_dlg_param.vstartup_start,
813 pipe_ctx->pipe_dlg_param.vupdate_offset,
814 pipe_ctx->pipe_dlg_param.vupdate_width,
2281 &pipe_ctx->pipe_dlg_param);
2465 pipe_ctx->pipe_dlg_param.vready_offset,
2466 pipe_ctx->pipe_dlg_param.vstartup_start,
2467 pipe_ctx->pipe_dlg_param.vupdate_offset,
2468 pipe_ctx->pipe_dlg_param.vupdate_width);
3130 pipe_ctx->pipe_dlg_param.vstartup_start + 1
    [all...]

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