| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_nv04.c | 212 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; local in function:setPLL_double_highregs
219 /* model specific additions to generic pll1 and pll2 set up above */
221 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
236 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
238 if (oldpll1 == pll1 && oldpll2 == pll2)
272 nvkm_wr32(device, reg1, pll1);
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| stih407-clock.dtsi | 109 clk_s_c0_pll1: clk-s-c0-pll1 {
111 compatible = "st,clkgen-pll1-c0";
|
| stih410-clock.dtsi | 109 clk_s_c0_pll1: clk-s-c0-pll1 {
111 compatible = "st,clkgen-pll1-c0";
|
| stih418-clock.dtsi | 110 clk_s_c0_pll1: clk-s-c0-pll1 {
112 compatible = "st,clkgen-pll1-c0";
|
| dove-cubox.dts | 101 /* connect xtal input as source of pll0 and pll1 */
|
| dra72x.dtsi | 72 reg-names = "dss", "pll1_clkctrl", "pll1";
|
| dra74x.dtsi | 138 reg-names = "dss", "pll1_clkctrl", "pll1",
|
| ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
219 pll1: pll1@0 { label in label:src
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
230 clocks = <&pll1>;
|
| da850.dtsi | 695 pll1: clock-controller@21a000 { label
696 compatible = "ti,da850-pll1";
|
| r8a73a4.dtsi | 484 clock-output-names = "main", "pll0", "pll1", "pll2",
|
| sh73a0.dtsi | 651 clock-output-names = "main", "pll0", "pll1", "pll2",
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_hw.c | 136 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
144 pllvals->log2P = (pll1 >> 16) & 0x7;
150 if (!(pll1 & 0x1100))
153 pllvals->NM1 = pll1 & 0xffff;
158 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
159 pllvals->M2 = (pll1 >> 4) & 0x7;
160 pllvals->N2 = ((pll1 >> 21) & 0x18) |
161 ((pll1 >> 19) & 0x7);
174 uint32_t reg1, pll1, pll2 = 0; local in function:nouveau_hw_get_pllvals
182 pll1 = nvif_rd32(device, reg1)
[all...] |
| /src/sys/arch/hpcmips/dev/ |
| mq200priv.h | 46 int pll1, pll2, pll3; member in struct:mq200_clock_setting
|
| mq200subr.c | 239 mq200_set_pll(sc, MQ200_CLOCK_PLL1, clock->pll1);
325 if (clock->pll1 == 0) {
326 DPRINTF("PLL1 disable\n");
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dpll_mgr.h | 197 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
|
| intel_dpll_mgr.c | 1559 temp |= pll->state.hw_state.pll1;
1689 hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1));
1690 hw_state->pll1 &= PORT_PLL_N_MASK;
1851 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
1932 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1937 hw_state->pll1,
|
| intel_ddi.c | 1728 clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
|
| intel_display.c | 13680 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
|
| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/ |
| k3-j721e-main.dtsi | 375 wiz0_pll1_refclk: pll1-refclk {
435 wiz1_pll1_refclk: pll1-refclk {
495 wiz2_pll1_refclk: pll1-refclk {
555 wiz3_pll1_refclk: pll1-refclk {
|
| k3-j7200-main.dtsi | 557 wiz0_pll1_refclk: pll1-refclk {
|
