| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/devinit/ |
| nouveau_nvkm_subdev_devinit_nv04.c | 213 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; local in function:setPLL_double_highregs
219 /* model specific additions to generic pll1 and pll2 set up above */
223 pll2 = 0;
232 pll2 |= 0x011f;
238 if (oldpll1 == pll1 && oldpll2 == pll2)
271 nvkm_wr32(device, reg2, pll2);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/ |
| nouveau_dispnv04_hw.c | 137 uint32_t pll2, struct nvkm_pll_vals *pllvals)
141 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
148 pllvals->NM1 = pll2 & 0xffff;
151 pllvals->NM2 = pll2 >> 16;
154 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
155 pllvals->NM2 = pll2 & 0xffff;
174 uint32_t reg1, pll1, pll2 = 0; local in function:nouveau_hw_get_pllvals
184 pll2 = nvif_rd32(device, reg1 + 4);
188 pll2 = nvif_rd32(device, reg2);
197 pll2 = 0
[all...] |
| /src/sys/arch/hpcmips/dev/ |
| mq200priv.h | 46 int pll1, pll2, pll3; member in struct:mq200_clock_setting
|
| mq200subr.c | 240 mq200_set_pll(sc, MQ200_CLOCK_PLL2, clock->pll2);
330 if (clock->pll2 == 0) {
331 DPRINTF("PLL2 disable\n");
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dpll_mgr.h | 197 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member in struct:intel_dpll_hw_state
|
| intel_dpll_mgr.c | 1565 temp |= pll->state.hw_state.pll2;
1692 hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2));
1693 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1852 dpll_hw_state->pll2 = clk_div->m2_frac;
1932 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
1938 hw_state->pll2,
|
| intel_ddi.c | 1727 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;
|
| intel_display.c | 13681 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
|
| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| ste-nomadik-stn8815.dtsi | 196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
242 pll2: pll2@0 { label in label:src
253 clocks = <&pll2>;
268 clocks = <&pll2>;
276 clocks = <&pll2>;
|
| dra74x.dtsi | 139 "pll2_clkctrl", "pll2";
|
| r8a73a4.dtsi | 484 clock-output-names = "main", "pll0", "pll1", "pll2",
|
| sh73a0.dtsi | 651 clock-output-names = "main", "pll0", "pll1", "pll2",
|
