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    Searched refs:reg_num (Results 1 - 19 of 19) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/
amdgpu_irq_service_dce120.c 110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
111 .enable_reg = SRI(reg1, block, reg_num),\
113 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
115 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
116 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
118 .ack_reg = SRI(reg2, block, reg_num),\
120 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
122 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
124 #define hpd_int_entry(reg_num)\
125 [DC_IRQ_SOURCE_HPD1 + reg_num] = {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/
amdgpu_irq_service_dcn10.c 191 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
192 .enable_reg = SRI(reg1, block, reg_num),\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
199 .ack_reg = SRI(reg2, block, reg_num),\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205 #define hpd_int_entry(reg_num)\
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/
amdgpu_irq_service_dcn20.c 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
194 .enable_reg = SRI(reg1, block, reg_num),\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
201 .ack_reg = SRI(reg2, block, reg_num),\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
209 #define hpd_int_entry(reg_num)\
210 [DC_IRQ_SOURCE_HPD1 + reg_num] = {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/
amdgpu_irq_service_dcn21.c 189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
190 .enable_reg = SRI(reg1, block, reg_num),\
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
197 .ack_reg = SRI(reg2, block, reg_num),\
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205 #define hpd_int_entry(reg_num)\
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
amdgpu_irq_service_dce110.c 96 #define hpd_int_entry(reg_num)\
97 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
98 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
104 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
107 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
111 #define hpd_rx_int_entry(reg_num)\
112 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
113 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
118 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
121 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/
amdgpu_irq_service_dce80.c 99 #define hpd_int_entry(reg_num)\
100 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
101 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
107 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
110 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
114 #define hpd_rx_int_entry(reg_num)\
115 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
116 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
121 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
124 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,
    [all...]
  /src/sys/dev/pci/
unichromehw.h 255 int reg_num; member in struct:iga1_hor_total
261 int reg_num; member in struct:iga1_hor_addr
267 int reg_num; member in struct:iga1_hor_blank_start
273 int reg_num; member in struct:iga1_hor_blank_end
279 int reg_num; member in struct:iga1_hor_sync_start
285 int reg_num; member in struct:iga1_hor_sync_end
291 int reg_num; member in struct:iga1_ver_total
297 int reg_num; member in struct:iga1_ver_addr
303 int reg_num; member in struct:iga1_ver_blank_start
309 int reg_num; member in struct:iga1_ver_blank_end
315 int reg_num; member in struct:iga1_ver_sync_start
321 int reg_num; member in struct:iga1_ver_sync_end
332 int reg_num; member in struct:iga2_shadow_hor_total
338 int reg_num; member in struct:iga2_shadow_hor_blank_end
345 int reg_num; member in struct:iga2_shadow_ver_total
351 int reg_num; member in struct:iga2_shadow_ver_addr
357 int reg_num; member in struct:iga2_shadow_ver_blank_start
363 int reg_num; member in struct:iga2_shadow_ver_blank_end
369 int reg_num; member in struct:iga2_shadow_ver_sync_start
375 int reg_num; member in struct:iga2_shadow_ver_sync_end
385 int reg_num; member in struct:iga2_hor_total
391 int reg_num; member in struct:iga2_hor_addr
397 int reg_num; member in struct:iga2_hor_blank_start
403 int reg_num; member in struct:iga2_hor_blank_end
409 int reg_num; member in struct:iga2_hor_sync_start
415 int reg_num; member in struct:iga2_hor_sync_end
421 int reg_num; member in struct:iga2_ver_total
427 int reg_num; member in struct:iga2_ver_addr
433 int reg_num; member in struct:iga2_ver_blank_start
439 int reg_num; member in struct:iga2_ver_blank_end
445 int reg_num; member in struct:iga2_ver_sync_start
451 int reg_num; member in struct:iga2_ver_sync_end
457 int reg_num; member in struct:iga1_offset
463 int reg_num; member in struct:iga2_offset
474 int reg_num; member in struct:iga1_fetch_count
480 int reg_num; member in struct:iga2_fetch_count
491 int reg_num; member in struct:iga1_starting_addr
496 int reg_num; member in struct:iga2_starting_addr
507 int reg_num; member in struct:lcd_pwd_seq_td0
512 int reg_num; member in struct:lcd_pwd_seq_td1
517 int reg_num; member in struct:lcd_pwd_seq_td2
522 int reg_num; member in struct:lcd_pwd_seq_td3
535 int reg_num; member in struct:_lcd_hor_scaling_factor
540 int reg_num; member in struct:_lcd_ver_scaling_factor
573 int reg_num; member in struct:iga1_fifo_depth_select
578 int reg_num; member in struct:iga1_fifo_threshold_select
583 int reg_num; member in struct:iga1_fifo_high_threshold_select
588 int reg_num; member in struct:iga1_display_queue_expire_num
593 int reg_num; member in struct:iga2_fifo_depth_select
598 int reg_num; member in struct:iga2_fifo_threshold_select
603 int reg_num; member in struct:iga2_fifo_high_threshold_select
608 int reg_num; member in struct:iga2_display_queue_expire_num
    [all...]
unichromefb.c 825 regnum = iga1_crtc_reg.hor_total.reg_num;
831 regnum = iga1_crtc_reg.hor_addr.reg_num;
837 regnum = iga1_crtc_reg.hor_blank_start.reg_num;
844 regnum = iga1_crtc_reg.hor_blank_end.reg_num;
850 regnum = iga1_crtc_reg.hor_sync_start.reg_num;
857 regnum = iga1_crtc_reg.hor_sync_end.reg_num;
863 regnum = iga1_crtc_reg.ver_total.reg_num;
869 regnum = iga1_crtc_reg.ver_addr.reg_num;
875 regnum = iga1_crtc_reg.ver_blank_start.reg_num;
882 regnum = iga1_crtc_reg.ver_blank_end.reg_num;
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
dm_services.h 185 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\
188 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
189 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
191 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\
195 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
196 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
amdgpu_hw_factory_dce120.c 48 #define reg_num 0 macro
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
amdgpu_hw_factory_dcn10.c 49 #define reg_num 0 macro
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
amdgpu_hw_factory_dcn20.c 55 #define reg_num 0 macro
amdgpu_hw_translate_dcn20.c 52 #define reg_num 0 macro
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
amdgpu_hw_factory_dcn21.c 53 #define reg_num 0 macro
amdgpu_hw_translate_dcn21.c 52 #define reg_num 0 macro
  /src/sys/dev/pci/cxgb/
cxgb_ioctl.h 236 uint32_t reg_num; member in struct:mii_data
  /src/sys/external/bsd/drm2/dist/drm/amd/display/include/
grph_object_ctrl_defs.h 278 unsigned char reg_num; member in struct:ext_hdmi_settings
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
amdgpu_dc_link.c 1609 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1621 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1633 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1645 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1663 if (settings->reg_num > 9)
1668 for (i = 0; i < settings->reg_num; i++) {
1728 for (i = 0; i < settings->reg_num; i++) {
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen.c 4162 u32 dws, data, i, j, k, reg_num; local in function:sumo_rlc_init
4304 reg_num = cs_data[i].section[j].reg_count;
4313 data = 0x08000000 | (reg_num * 4);
4317 for (k = 0; k < reg_num; k++) {
4321 reg_list_mc_addr += reg_num * 4;
4322 reg_list_blk_index += reg_num;

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