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    Searched refs:sclk_setting (Results 1 - 3 of 3) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vegam_smumgr.c 722 uint32_t clock, SMU_SclkSetting *sclk_setting)
733 sclk_setting->SclkFrequency = clock;
737 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
738 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
739 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
740 sclk_setting->PllRange = dividers.ucSclkPllRange;
741 sclk_setting->Sclk_slew_rate = 0x400;
742 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
743 sclk_setting->Pcc_down_slew_rate = 0xffff;
744 sclk_setting->SSc_En = dividers.ucSscEnable
    [all...]
amdgpu_polaris10_smumgr.c 847 uint32_t clock, SMU_SclkSetting *sclk_setting)
858 sclk_setting->SclkFrequency = clock;
862 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
863 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
864 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
865 sclk_setting->PllRange = dividers.ucSclkPllRange;
866 sclk_setting->Sclk_slew_rate = 0x400;
867 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
868 sclk_setting->Pcc_down_slew_rate = 0xffff;
869 sclk_setting->SSc_En = dividers.ucSscEnable
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/
atomfirmware.h 2644 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; member in union:dynamic_memory_settings_parameters_v2_1

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