| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_pm4_headers.h | 77 uint32_t sh_mem_ape1_base; member in struct:pm4_map_process
128 uint32_t sh_mem_ape1_base; member in struct:pm4_map_process_scratch_kv
|
| kfd_device_queue_manager_v10.c | 78 qpd->sh_mem_ape1_base = 0;
|
| kfd_device_queue_manager_v9.c | 75 qpd->sh_mem_ape1_base = 0;
|
| kfd_device_queue_manager_cik.c | 136 qpd->sh_mem_ape1_base = 0;
170 qpd->sh_mem_ape1_base = 0;
|
| kfd_device_queue_manager_vi.c | 176 qpd->sh_mem_ape1_base = 0;
218 qpd->sh_mem_ape1_base = 0;
|
| kfd_packet_manager_vi.c | 68 packet->sh_mem_ape1_base = qpd->sh_mem_ape1_base;
|
| kfd_pm4_headers_vi.h | 175 uint32_t sh_mem_ape1_base; member in struct:pm4_mes_map_process
|
| kfd_device_queue_manager.c | 135 qpd->sh_mem_ape1_base,
1498 qpd->sh_mem_ape1_base = 1;
1502 * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
1503 * SH_MEM_APE1_BASE[31:0], 0x0000 }
1520 qpd->sh_mem_ape1_base = base >> 16;
1536 qpd->sh_mem_config, qpd->sh_mem_ape1_base,
|
| kfd_priv.h | 569 uint32_t sh_mem_ape1_base; member in struct:qcm_process_device
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_amdkfd_gfx_v9.h | 29 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
|
| amdgpu_amdkfd_gfx_v7.c | 158 uint32_t sh_mem_ape1_base,
167 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
|
| amdgpu_amdkfd_gfx_v8.c | 115 uint32_t sh_mem_ape1_base,
124 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
|
| amdgpu_amdkfd_gfx_v10.c | 131 uint32_t sh_mem_ape1_base,
|
| amdgpu_amdkfd_gfx_v9.c | 127 uint32_t sh_mem_ape1_base,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| kgd_kfd_interface.h | 248 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
|
