| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/ |
| irq_service.h | 57 uint32_t status_reg; member in struct:irq_source_info
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 52 uint32_t addr = info->status_reg;
107 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
121 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
135 .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/ |
| amdgpu_irq_service_dce120.c | 51 uint32_t addr = info->status_reg;
129 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
138 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
146 .status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/ |
| amdgpu_irq_service_dce80.c | 51 uint32_t addr = info->status_reg;
110 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
124 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
139 .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| execlist.c | 102 u32 status_reg = execlist_ring_mmio(vgpu->gvt, local in function:emulate_execlist_status
105 status.ldw = vgpu_vreg(vgpu, status_reg);
106 status.udw = vgpu_vreg(vgpu, status_reg + 4);
124 vgpu_vreg(vgpu, status_reg) = status.ldw;
125 vgpu_vreg(vgpu, status_reg + 4) = status.udw;
128 vgpu->id, status_reg, status.ldw, status.udw);
270 u32 status_reg = execlist_ring_mmio(vgpu->gvt, ring_id, local in function:get_next_execlist_slot
274 status.ldw = vgpu_vreg(vgpu, status_reg);
275 status.udw = vgpu_vreg(vgpu, status_reg + 4);
|
| handlers.c | 700 i915_reg_t status_reg; local in function:dp_tp_ctl_mmio_write
709 status_reg = DP_TP_STATUS(index);
710 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
|
| /src/sys/dev/pci/ |
| twa.c | 1064 uint32_t status_reg; local in function:twa_start
1087 status_reg = twa_inl(sc, TWA_STATUS_REGISTER_OFFSET);
1088 if ((error = twa_check_ctlr_state(sc, status_reg)))
1091 if (status_reg & TWA_STATUS_COMMAND_QUEUE_FULL) {
1137 uint32_t status_reg; local in function:twa_drain_response_queue
1140 status_reg = twa_inl(sc, TWA_STATUS_REGISTER_OFFSET);
1141 if (twa_check_ctlr_state(sc, status_reg))
1143 if (status_reg & TWA_STATUS_RESPONSE_QUEUE_EMPTY)
1359 uint32_t status_reg; local in function:twa_done
1362 status_reg = twa_inl(sc, TWA_STATUS_REGISTER_OFFSET)
1880 uint32_t status_reg; local in function:twa_intr
2627 uint32_t status_reg; local in function:twa_soft_reset
2678 uint32_t status_reg; local in function:twa_wait_status
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_cm.c | 646 uint32_t status_reg = 0; local in function:dpp1_degamma_ram_inuse
650 &status_reg);
652 if (status_reg == 9) {
655 } else if (status_reg == 10) {
738 uint32_t status_reg = 0; local in function:dpp1_ingamma_ram_inuse
742 &status_reg);
745 if (status_reg == 1 || status_reg == 3 || status_reg == 4) {
749 } else if (status_reg == 2 || status_reg == 5 || status_reg == 6)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/ |
| amdgpu_irq_service_dcn10.c | 132 uint32_t addr = info->status_reg;
210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/ |
| amdgpu_irq_service_dcn20.c | 132 uint32_t addr = info->status_reg;
214 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
223 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/ |
| amdgpu_irq_service_dcn21.c | 133 uint32_t addr = info->status_reg;
210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
|
| /src/sys/dev/i2c/ |
| sht3x.c | 521 uint16_t status_reg; local in function:sht3x_take_periodic_measurement
531 error = sht3x_get_status_register(sc, &status_reg, true);
539 if (status_reg & SHT3X_RESET_DETECTED) {
545 sc->sc_heateron = status_reg & SHT3X_HEATER_STATUS;
1156 uint16_t status_reg; local in function:sht3x_attach
1157 error = sht3x_get_status_register(sc, &status_reg, true);
1165 device_xname(sc->sc_dev), status_reg));
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dpp_cm.c | 74 uint32_t status_reg = 0; local in function:dpp2_degamma_ram_inuse
78 &status_reg);
80 if (status_reg == 3) {
83 } else if (status_reg == 4) {
|
| /src/sys/arch/riscv/starfive/ |
| jh7110_clkc.c | 1006 const bus_size_t status_reg = sc->sc_reset_status + off; local in function:jh7110_clkc_reset_set
1019 status = RD4(sc, status_reg);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_vi.c | 791 u32 cntl_reg, u32 status_reg)
814 tmp = RREG32_SMC(status_reg);
|
| amdgpu_cik.c | 1384 u32 cntl_reg, u32 status_reg)
1403 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen.c | 1151 u32 cntl_reg, u32 status_reg)
1164 if (RREG32(status_reg) & DCLK_STATUS)
|
| radeon_cik.c | 9491 u32 cntl_reg, u32 status_reg)
9508 if (RREG32_SMC(status_reg) & DCLK_STATUS)
|
