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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/
nouveau_nvkm_subdev_fb_nv25.c 36 struct nvkm_fb_tile *tile)
40 if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
41 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */
42 else tile->zcomp = 0x00200000; /* Z24S8 */
43 tile->zcomp |= tile->tag->offset;
45 tile->zcomp |= 0x01000000;
53 .tile.regions = 8,
54 .tile.init = nv20_fb_tile_init,
55 .tile.comp = nv25_fb_tile_comp
    [all...]
nouveau_nvkm_subdev_fb_nv20.c 36 u32 flags, struct nvkm_fb_tile *tile)
38 tile->addr = 0x00000001 | addr;
39 tile->limit = max(1u, addr + size) - 1;
40 tile->pitch = pitch;
42 fb->func->tile.comp(fb, i, size, flags, tile);
43 tile->addr |= 2;
49 struct nvkm_fb_tile *tile)
53 if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
54 if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 *
    [all...]
nouveau_nvkm_subdev_fb_nv46.c 36 u32 flags, struct nvkm_fb_tile *tile)
39 if (!(flags & 4)) tile->addr = (0 << 3);
40 else tile->addr = (1 << 3);
42 tile->addr |= 0x00000001; /* mode = vram */
43 tile->addr |= addr;
44 tile->limit = max(1u, addr + size) - 1;
45 tile->pitch = pitch;
51 .tile.regions = 15,
52 .tile.init = nv46_fb_tile_init,
53 .tile.fini = nv20_fb_tile_fini
    [all...]
nouveau_nvkm_subdev_fb_nv10.c 36 u32 flags, struct nvkm_fb_tile *tile)
38 tile->addr = 0x80000000 | addr;
39 tile->limit = max(1u, addr + size) - 1;
40 tile->pitch = pitch;
44 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
46 tile->addr = 0;
47 tile->limit = 0;
48 tile->pitch = 0;
49 tile->zcomp = 0;
53 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
    [all...]
nouveau_nvkm_subdev_fb_nv1a.c 36 .tile.regions = 8,
37 .tile.init = nv10_fb_tile_init,
38 .tile.fini = nv10_fb_tile_fini,
39 .tile.prog = nv10_fb_tile_prog,
nouveau_nvkm_subdev_fb_nv4e.c 37 .tile.regions = 12,
38 .tile.init = nv46_fb_tile_init,
39 .tile.fini = nv20_fb_tile_fini,
40 .tile.prog = nv44_fb_tile_prog,
nouveau_nvkm_subdev_fb_nv47.c 38 .tile.regions = 15,
39 .tile.init = nv30_fb_tile_init,
40 .tile.comp = nv40_fb_tile_comp,
41 .tile.fini = nv20_fb_tile_fini,
42 .tile.prog = nv41_fb_tile_prog,
nouveau_nvkm_subdev_fb_nv49.c 38 .tile.regions = 15,
39 .tile.init = nv30_fb_tile_init,
40 .tile.comp = nv40_fb_tile_comp,
41 .tile.fini = nv20_fb_tile_fini,
42 .tile.prog = nv41_fb_tile_prog,
nouveau_nvkm_subdev_fb_nv35.c 36 struct nvkm_fb_tile *tile)
40 if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
41 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */
42 else tile->zcomp |= 0x08000000; /* Z24S8 */
43 tile->zcomp |= ((tile->tag->offset ) >> 6);
44 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13;
46 tile->zcomp |= 0x40000000;
55 .tile.regions = 8
    [all...]
nouveau_nvkm_subdev_fb_nv36.c 36 struct nvkm_fb_tile *tile)
40 if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
41 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */
42 else tile->zcomp |= 0x20000000; /* Z24S8 */
43 tile->zcomp |= ((tile->tag->offset ) >> 6);
44 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14;
46 tile->zcomp |= 0x80000000;
55 .tile.regions = 8
    [all...]
nouveau_nvkm_subdev_fb_nv40.c 36 struct nvkm_fb_tile *tile)
41 !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) {
42 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */
43 tile->zcomp |= ((tile->tag->offset ) >> 8);
44 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13;
46 tile->zcomp |= 0x40000000;
61 .tile.regions = 8,
62 .tile.init = nv30_fb_tile_init
    [all...]
nouveau_nvkm_subdev_fb_nv44.c 36 u32 flags, struct nvkm_fb_tile *tile)
38 tile->addr = 0x00000001; /* mode = vram */
39 tile->addr |= addr;
40 tile->limit = max(1u, addr + size) - 1;
41 tile->pitch = pitch;
45 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
48 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit);
49 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch);
50 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr);
65 .tile.regions = 12
    [all...]
nouveau_nvkm_subdev_fb_nv41.c 35 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
38 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit);
39 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch);
40 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr);
42 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp);
55 .tile.regions = 12,
56 .tile.init = nv30_fb_tile_init,
57 .tile.comp = nv40_fb_tile_comp,
58 .tile.fini = nv20_fb_tile_fini,
59 .tile.prog = nv41_fb_tile_prog
    [all...]
nouveau_nvkm_subdev_fb_nv30.c 36 u32 flags, struct nvkm_fb_tile *tile)
40 tile->addr = (0 << 4);
42 if (fb->func->tile.comp) /* z compression */
43 fb->func->tile.comp(fb, i, size, flags, tile);
44 tile->addr = (1 << 4);
47 tile->addr |= 0x00000001; /* enable */
48 tile->addr |= addr;
49 tile->limit = max(1u, addr + size) - 1;
50 tile->pitch = pitch
    [all...]
nouveau_nvkm_subdev_fb_base.c 40 nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile)
42 fb->func->tile.fini(fb, region, tile);
47 u32 pitch, u32 flags, struct nvkm_fb_tile *tile)
49 fb->func->tile.init(fb, region, addr, size, pitch, flags, tile);
53 nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile)
56 if (fb->func->tile.prog) {
57 fb->func->tile.prog(fb, region, tile);
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
nouveau_nvkm_engine_gr_nv44.c 36 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
49 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
50 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
51 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
58 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
59 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
60 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
61 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
62 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
63 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr)
    [all...]
nouveau_nvkm_engine_gr_base.c 70 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile)
73 if (gr->func->tile)
74 gr->func->tile(gr, region, tile);
175 .tile = nvkm_gr_tile,
nouveau_nvkm_engine_gr_nv40.c 178 nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
194 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
195 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
196 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
197 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
198 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
199 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
203 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
204 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
209 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp)
    [all...]
nouveau_nvkm_engine_gr_nv15.c 35 .tile = nv10_gr_tile,
nouveau_nvkm_engine_gr_nv17.c 35 .tile = nv10_gr_tile,
priv.h 23 void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); member in struct:nvkm_gr_func
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/
i915_gem_mman.c 24 struct tile { struct
38 static u64 tiled_offset(const struct tile *tile, u64 v)
42 if (tile->tiling == I915_TILING_NONE)
45 y = div64_u64_rem(v, tile->stride, &x);
46 v = div64_u64_rem(y, tile->height, &y) * tile->stride * tile->height;
48 if (tile->tiling == I915_TILING_X) {
49 v += y * tile->width
340 struct tile tile; local in function:igt_partial_tiling
358 struct tile tile; local in function:igt_partial_tiling
477 struct tile tile; local in function:igt_smoke_tiling
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v7_0.c 1038 uint32_t *tile, *macrotile; local in function:gfx_v7_0_tiling_mode_table_init
1040 tile = adev->gfx.config.tile_mode_array;
1057 tile[reg_offset] = 0;
1063 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1067 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1071 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1075 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1079 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083 tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1086 tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/
nouveau_bo.c 61 int i = reg - drm->tile.reg;
63 struct nvkm_fb_tile *tile = &fb->tile.region[i]; local in function:nv10_bo_update_tile_region
67 if (tile->pitch)
68 nvkm_fb_tile_fini(fb, i, tile);
71 nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile);
73 nvkm_fb_tile_prog(fb, i, tile);
80 struct nouveau_drm_tile *tile = &drm->tile.reg[i]; local in function:nv10_bo_get_tile_region
82 spin_lock(&drm->tile.lock)
114 struct nouveau_drm_tile *tile, *found = NULL; local in function:nv10_bo_set_tiling
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/core/
engine.h 27 void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); member in struct:nvkm_engine_func

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