| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_vmid.c | 37 vmid->regs->reg
40 vmid->ctx
44 vmid->shifts->field_name, vmid->masks->field_name
46 static void dcn20_wait_for_vmid_ready(struct dcn20_vmid *vmid)
78 void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config)
100 dcn20_wait_for_vmid_ready(vmid);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| cik_event_interrupt.c | 41 unsigned int vmid; local in function:cik_event_interrupt_isr
46 * VMID and PASID are not written into ih_ring_entry
57 vmid = f2g->read_vmid_from_vmfault_reg(dev->kgd);
58 ret = f2g->get_atc_vmid_pasid_mapping_info(dev->kgd, vmid, &pasid);
61 tmp_ihre->ring_id |= vmid << 8;
65 vmid >= dev->vm_info.first_vmid_kfd &&
66 vmid <= dev->vm_info.last_vmid_kfd;
70 vmid = (ihre->ring_id & 0x0000ff00) >> 8;
71 if (vmid < dev->vm_info.first_vmid_kfd ||
72 vmid > dev->vm_info.last_vmid_kfd
97 unsigned int vmid = (ihre->ring_id & 0x0000ff00) >> 8; local in function:cik_event_interrupt_wq
[all...] |
| kfd_int_process_v9.c | 38 uint16_t source_id, client_id, pasid, vmid; local in function:event_interrupt_isr_v9
42 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
43 if (vmid < dev->vm_info.first_vmid_kfd ||
44 vmid > dev->vm_info.last_vmid_kfd)
62 pasid = dev->dqm->vmid_pasid[vmid];
69 pr_debug("client id 0x%x, source id %d, vmid %d, pasid 0x%x. raw data:\n",
70 client_id, source_id, vmid, pasid);
94 uint16_t source_id, client_id, pasid, vmid; local in function:event_interrupt_wq_v9
100 vmid = SOC15_VMID_FROM_IH_ENTRY(ih_ring_entry);
117 info.vmid = vmid
[all...] |
| kfd_queue.c | 43 pr_debug("Queue Process Vmid: %u\n", q->vmid);
60 pr_debug("Queue Process Vmid: %u\n", q->properties.vmid);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| cik.h | 32 u32 me, u32 pipe, u32 queue, u32 vmid);
|
| si.h | 32 u32 me, u32 pipe, u32 queue, u32 vmid);
|
| vi.h | 32 u32 me, u32 pipe, u32 queue, u32 vmid);
|
| gfxhub_v1_0.h | 35 void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
| gfxhub_v2_0.h | 36 void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
| mmhub_v2_0.h | 36 void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
| nv.h | 32 u32 me, u32 pipe, u32 queue, u32 vmid);
|
| mmhub_v9_4.h | 39 void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
| amdgpu_amdkfd_gfx_v9.h | 27 void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
32 unsigned int vmid);
64 uint8_t vmid, uint16_t *p_pasid);
|
| amdgpu_gmc.h | 95 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
101 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
103 /* Change the VMID -> PASID mapping */
104 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
226 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
230 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
231 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)
[all...] |
| jpeg_v2_0.h | 38 unsigned vmid, uint64_t pd_addr);
|
| mmhub_v1_0.h | 41 void mmhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
|
| amdgpu_job.h | 40 #define AMDGPU_JOB_GET_VMID(job) ((job) ? (job)->vmid : 0)
56 unsigned vmid; member in struct:amdgpu_job
|
| vcn_v2_0.h | 39 unsigned vmid, uint64_t pd_addr);
52 unsigned int vmid, uint64_t pd_addr);
|
| amdgpu_amdkfd_gfx_v9.c | 84 uint32_t queue, uint32_t vmid)
89 soc15_grbm_select(adev, mec, pipe, queue, vmid);
125 void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
133 lock_srbm(kgd, 0, 0, 0, vmid);
143 unsigned int vmid)
159 * for ATC add 16 to VMID for mmhub, for IH different registers.
163 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
169 (1U << vmid)))
174 1U << vmid);
176 /* Mapping vmid to pasid also for IH block *
[all...] |
| amdgpu_amdkfd_gfx_v10.c | 88 uint32_t queue, uint32_t vmid)
93 nv_grbm_select(adev, mec, pipe, queue, vmid);
129 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
137 lock_srbm(kgd, 0, 0, 0, vmid);
147 unsigned int vmid)
161 pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping);
163 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid);
164 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,
172 (1U << vmid)))
[all...] |
| amdgpu_amdkfd_gfx_v7.c | 82 uint32_t vmid:4; member in struct:TCP_WATCH_CNTL_BITS::__anondd4ee9010408
123 uint32_t queue, uint32_t vmid)
126 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
156 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
164 lock_srbm(kgd, 0, 0, 0, vmid);
175 unsigned int vmid)
188 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
190 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
192 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
[all...] |
| amdgpu_gmc_v10_0.c | 166 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
169 entry->src_id, entry->ring_id, entry->vmid,
210 static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
215 /* invalidate using legacy mode on vmid*/
217 PER_VMID_INVALIDATE_REQ, 1 << vmid);
247 uint8_t vmid, uint16_t *p_pasid)
252 + vmid);
260 * VMID 0 is the physical GPU addresses as used by the kernel.
265 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
270 u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type)
417 int vmid, i; local in function:gmc_v10_0_flush_gpu_tlb_pasid
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/modules/vmid/ |
| vmid.c | 1 /* $NetBSD: vmid.c,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */
29 __KERNEL_RCSID(0, "$NetBSD: vmid.c,v 1.2 2021/12/18 23:45:08 riastradh Exp $");
46 static void add_ptb_to_table(struct core_vmid *core_vmid, unsigned int vmid, uint64_t ptb)
48 core_vmid->ptb_assigned_to_vmid[vmid] = ptb;
52 static void clear_entry_from_vmid_table(struct core_vmid *core_vmid, unsigned int vmid)
54 core_vmid->ptb_assigned_to_vmid[vmid] = 0;
70 // Return value of -1 indicates vmid table unitialized or ptb dne in the table
83 // Expected to be called only when there's an available vmid
99 unsigned int vmid = 0; local in function:mod_vmid_get_for_ptb
101 // Physical address gets vmid
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| kgd_kfd_interface.h | 53 uint32_t vmid; member in struct:kfd_vm_fault_info
118 /* Bit n == 1 means VMID n is available for KFD. */
200 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
224 * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
229 * @set_vm_context_page_table_base: Program page table base for a VMID
233 * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
235 * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
236 * IH ring entry. This function allows the KFD ISR to get the VMID
247 void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
252 unsigned int vmid);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc_vm_helper.c | 60 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid)
62 dc->hwss.init_vm_ctx(dc->hwseq, dc, va_config, vmid);
|
