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  /src/sys/arch/arm/nvidia/
tegra_pciereg.h 60 #define AFI_PEXn_STATUS_REG(n) (0x114 + (n) * 8)
tegra124_xusbpadreg.h 101 #define XUSB_PADCTL_IOPHY_MISC_PAD_P3_CTL4_REG 0x114
  /src/sys/arch/powerpc/include/
spr.h 140 #define SPR_SPRG4 0x114 /* E4.. SPR General 4 */
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_2_d.h 96 #define ixUVD_MIF_RECON1_ADDR_CONFIG 0x114
  /src/sys/dev/pcmcia/
if_cnwreg.h 68 #define CNW_EREG_ASCC 0x114
  /src/sys/arch/arm/broadcom/
bcm2835_cm.h 148 #define CM_LOCK 0x114
  /src/sys/arch/arm/ixp12x0/
ixp12x0_pcireg.h 107 #define DRAM_ADDR_SIZE_1 0x114
  /src/sys/arch/arm/marvell/
mvsocreg.h 123 #define MVSOC_MLMB_MLMBIMR 0x114 /*Mb-L to Mb Bridge Intr Mask */
  /src/sys/arch/sh3/include/
pcicreg.h 70 #define SH4_PCIINT (SH4_PCIC+0x114) /* 32bit */
  /src/sys/dev/usb/
if_smscreg.h 144 #define SMSC_MII_ADDR 0x114
  /src/external/gpl3/gdb.old/dist/gdb/testsuite/gdb.btrace/
i386-ptwrite.S 251 .long 0x114 # DW_AT_abstract_origin
276 .long 0x114 # DW_AT_sibling
287 .long 0x114 # DW_AT_abstract_origin
300 .uleb128 0x9 # (DIE (0x114) DW_TAG_subprogram)
315 .byte 0 # end of children of DIE 0x114
  /src/external/gpl3/gdb/dist/gdb/testsuite/gdb.btrace/
i386-ptwrite.S 251 .long 0x114 # DW_AT_abstract_origin
276 .long 0x114 # DW_AT_sibling
287 .long 0x114 # DW_AT_abstract_origin
300 .uleb128 0x9 # (DIE (0x114) DW_TAG_subprogram)
315 .byte 0 # end of children of DIE 0x114
  /src/sys/arch/amiga/amiga/
cc_registers.h 164 #define R_BPL2DAT 0x114
  /src/sys/arch/arm/apple/
apple_mbox.c 62 #define MBOX_I2A_CTRL 0x114
  /src/sys/arch/arm/footbridge/
dc21285reg.h 180 #define SDRAM_ADDRESS_SIZE_1 0x114
  /src/sys/arch/arm/imx/
imx23_clkctrlreg.h 276 #define HW_CLKCTRL_CLKSEQ_SET 0x114
  /src/sys/arch/arm/ti/
omap2_gpmcreg.h 84 #define GPMC_NAND_DATA_3 0x114
  /src/sys/arch/hpcmips/dev/
ite8181reg.h 95 #define ITE8181_GUI_CC1R0 0x114 /* Cursor Color 1 Reg. */
  /src/sys/dev/ic/
ahcisatareg.h 199 #define AHCI_P_IE(p) (0x114 + AHCI_P_OFFSET(p)) /* Interrupt enable */
  /src/sys/dev/pci/
cs4281reg.h 91 #define CS4281_DCC0 0x114 /* DMA Engine 0 Current Count Register */
  /src/sys/dev/sbus/
p9100reg.h 131 #define VID_HBFE 0x114 /* hblank falling edge */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_doorbell.h 130 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114,
  /src/external/gpl3/binutils/dist/gprofng/src/
hwc_arm64_amcc.h 81 { I("page_walk_l2_stage1_hit", 0x114, STXT("Page walk, L2 stage-1 hit")) },
  /src/external/gpl3/binutils.old/dist/gprofng/src/
hwc_arm64_amcc.h 81 { I("page_walk_l2_stage1_hit", 0x114, STXT("Page walk, L2 stage-1 hit")) },
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/nxp/imx/
imxrt1050-pinfunc.h 519 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_FLEXSPI_B_DATA1 0x114 0x304 0x4BC 0x0 0x1
520 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x114 0x304 0x4E0 0x1 0x2
521 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_LPUART3_TXD 0x114 0x304 0x53C 0x2 0x1
522 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x114 0x304 0x000 0x3 0x0
523 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x114 0x304 0x428 0x4 0x1
524 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x114 0x304 0x000 0x5 0x0
525 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x114 0x304 0x5F0 0x6 0x1
526 #define MXRT1050_IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x114 0x304 0x000 0x7 0x0

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