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  /src/sys/arch/arm/samsung/
mct_reg.h 51 #define MCT_G_INT_ENB 0x248 /* enable interrupts */
  /src/sys/dev/isa/
ioat66.c 67 int ioatbases[NSLAVES]={0x220,0x228,0x240,0x248,0x260,0x268};
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
am4.h 55 #define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
165 #define AM4_L3S_MMC3_CLKCTRL AM4_L3S_CLKCTRL_INDEX(0x248)
  /src/sys/arch/sparc64/dev/
ffbreg.h 168 #define FFB_FBC_BLENDC1 0x248
  /src/sys/dev/pci/
if_bwfm_pci.h 64 #define BWFM_PCI_CFGREG_PML1_SUB_CTRL1 0x248
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
keystone-k2hk.dtsi 109 reg = <0x248 0x4>;
112 gpio,syscon-dev = <&devctrl 0x248>;
keystone-k2l.dtsi 311 reg = <0x248 0x4>;
314 gpio,syscon-dev = <&devctrl 0x248>;
imx25-pinfunc.h 60 #define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x00 0x000
61 #define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x05 0x000
62 #define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x06 0x000
63 #define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x07 0x000
imx35-pinfunc.h 619 #define MX35_PAD_SD2_CMD__ESDHC2_CMD 0x248 0x6ac 0x000 0x0 0x0
620 #define MX35_PAD_SD2_CMD__I2C3_SCL 0x248 0x6ac 0x91c 0x1 0x2
621 #define MX35_PAD_SD2_CMD__ESDHC1_DAT4 0x248 0x6ac 0x804 0x2 0x0
622 #define MX35_PAD_SD2_CMD__IPU_CSI_D_2 0x248 0x6ac 0x938 0x3 0x2
623 #define MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4 0x248 0x6ac 0x9dc 0x4 0x0
624 #define MX35_PAD_SD2_CMD__GPIO2_0 0x248 0x6ac 0x868 0x5 0x2
625 #define MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1 0x248 0x6ac 0x000 0x6 0x0
626 #define MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC 0x248 0x6ac 0x928 0x7 0x3
imx6dl-pinfunc.h 796 #define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3
797 #define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1
798 #define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1
799 #define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0
800 #define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0
801 #define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2
802 #define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0
803 #define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0
imx6q-pinfunc.h 713 #define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
714 #define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
715 #define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
716 #define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
717 #define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
718 #define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
719 #define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
720 #define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
imx53-pinfunc.h 798 #define MX53_PAD_FEC_MDIO__FEC_MDIO 0x248 0x5c4 0x804 0x0 0x1
799 #define MX53_PAD_FEC_MDIO__GPIO1_22 0x248 0x5c4 0x000 0x1 0x0
800 #define MX53_PAD_FEC_MDIO__ESAI1_SCKR 0x248 0x5c4 0x7dc 0x2 0x0
801 #define MX53_PAD_FEC_MDIO__FEC_COL 0x248 0x5c4 0x800 0x3 0x1
802 #define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2 0x248 0x5c4 0x000 0x4 0x0
803 #define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3 0x248 0x5c4 0x000 0x5 0x0
804 #define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49 0x248 0x5c4 0x000 0x6 0x0
imx6sl-pinfunc.h 916 #define MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x248 0x550 0x000 0x0 0x0
917 #define MX6SL_PAD_SD1_DAT5__FEC_RX_DATA0 0x248 0x550 0x6f8 0x1 0x2
918 #define MX6SL_PAD_SD1_DAT5__KEY_ROW3 0x248 0x550 0x760 0x2 0x2
919 #define MX6SL_PAD_SD1_DAT5__EPDC_SDOED 0x248 0x550 0x000 0x3 0x0
920 #define MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x248 0x550 0x000 0x4 0x0
921 #define MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x248 0x550 0x814 0x4 0x5
922 #define MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x248 0x550 0x000 0x5 0x0
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pinctrl.dtsi 336 0x248 MODE_NITRO /* drdu3_id */
  /src/sys/arch/arm/nvidia/
tegra210_pinmux.c 207 TEGRA_PIN("pe6", 0x248, "rsvd0", "i2s5a", "pwm2", "rsvd3"),
  /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/brcm/
bcm7425.dtsi 541 reg = <0x1000 0x248>;
568 reg = <0x1000 0x248>;
bcm7435.dtsi 556 reg = <0x1000 0x248>;
583 reg = <0x1000 0x248>;
bcm7360.dtsi 449 reg = <0x1000 0x248>;
bcm7362.dtsi 445 reg = <0x1000 0x248>;
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
imx8mn-pinfunc.h 628 #define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
629 #define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
630 #define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
631 #define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
632 #define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x248 0x4B0 0x000 0x2 0x0
633 #define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x248 0x4B0 0x5E8 0x3 0x1
634 #define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
imx8mm-pinfunc.h 626 #define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
627 #define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
628 #define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
629 #define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
630 #define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
631 #define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
imx8mq-pinfunc.h 594 #define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
595 #define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
596 #define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
597 #define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
598 #define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
599 #define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
  /src/sys/arch/m68k/060sp/dist/
fplsp.doc 214 0x248: _060LSP__fabsd_
  /src/sys/arch/mips/cavium/dev/
octeon_gmxreg.h 74 #define GMX0_TX0_PAUSE_PKT_INTERVAL 0x248
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_0_d.h 169 #define ixCLIENT1_CK3 0x248

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