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  /src/sys/arch/aarch64/aarch64/
start.S 55 * x8 = currently loaded address
56 * x9 = (x8 + L2_SIZE - 1) & -L2_SIZE = new (aligned) loaded address
58 adrl x8, .header
60 add x9, x9, x8
62 cmp x8, x9
70 /* do memmove(x9, x8, x10) */
71 add x8, x8, x10
74 ldp x11, x12, [x8, #-16]!
88 adrl x8, __bss_start_
    [all...]
bus_space_asm_generic.S 39 lsl x8, x2, x8 /* offset <<= tag->bs_stride */
40 ldrb w0, [x1, x8]
49 lsl x8, x2, x8 /* offset <<= tag->bs_stride */
50 ldrh w0, [x1, x8]
59 lsl x8, x2, x8 /* offset <<= tag->bs_stride */
60 ldr w0, [x1, x8]
69 lsl x8, x2, x8 /* offset <<= tag->bs_stride *
    [all...]
cpufunc_asm_armv8.S 222 /* x8 = bit 63[ASID]48, 47[RES0]0 */
223 lsl x8, x0, #48
226 tlbi aside1is, x8
228 tlbi aside1, x8
237 /* x8 = bit 63[RES0]44, 43[VA(55:12)]0 */
238 ubfx x8, x0, #12, #44
241 tlbi vaae1is, x8
243 tlbi vaae1, x8
252 /* x8 = bit 63[RES0]44, 43[VA(55:12)]0 */
253 ubfx x8, x0, #12, #4
    [all...]
  /src/lib/libc/arch/aarch64/sys/
__vfork14.S 42 mov x8, x30
47 ret x8
  /src/sys/external/bsd/compiler_rt/dist/test/Unit/
floatundixf_test.c 71 if (test__floatundixf(0x8000008000000000ULL, 0x8.000008p+60))
73 if (test__floatundixf(0x8000000000000800ULL, 0x8.0000000000008p+60))
75 if (test__floatundixf(0x8000010000000000ULL, 0x8.00001p+60))
77 if (test__floatundixf(0x8000000000001000ULL, 0x8.000000000001p+60))
82 if (test__floatundixf(0x8000000000000001ULL, 0x8.000000000000001p+60L))
112 if (test__floatundixf(0x023479FD0E092DA1ULL, 0x8.D1E7F43824B684p+54L))
114 if (test__floatundixf(0x023479FD0E092DB0ULL, 0x8.D1E7f43824B6Cp+54L))
116 if (test__floatundixf(0x023479FD0E092DB8ULL, 0x8.D1E7F43824B6Ep+54L))
118 if (test__floatundixf(0x023479FD0E092DB6ULL, 0x8.D1E7F43824B6D8p+54L))
120 if (test__floatundixf(0x023479FD0E092DBFULL, 0x8.D1E7F43824B6FCp+54L)
    [all...]
floatdixf_test.c 111 if (test__floatdixf(0x023479FD0E092DA1LL, 0x8.D1E7F43824B684p+54L))
113 if (test__floatdixf(0x023479FD0E092DB0LL, 0x8.D1E7f43824B6Cp+54L))
115 if (test__floatdixf(0x023479FD0E092DB8LL, 0x8.D1E7F43824B6Ep+54L))
117 if (test__floatdixf(0x023479FD0E092DB6LL, 0x8.D1E7F43824B6D8p+54L))
119 if (test__floatdixf(0x023479FD0E092DBFLL, 0x8.D1E7F43824B6FCp+54L))
121 if (test__floatdixf(0x023479FD0E092DC1LL, 0x8.D1E7F43824B704p+54L))
123 if (test__floatdixf(0x023479FD0E092DC7LL, 0x8.D1E7F43824B71Cp+54L))
125 if (test__floatdixf(0x023479FD0E092DC8LL, 0x8.D1E7F43824B72p+54L))
127 if (test__floatdixf(0x023479FD0E092DCFLL, 0x8.D1E7F43824B73Cp+54L))
129 if (test__floatdixf(0x023479FD0E092DD0LL, 0x8.D1E7F43824B74p+54L)
    [all...]
  /src/sys/external/bsd/compiler_rt/dist/test/builtins/Unit/
floatundixf_test.c 71 if (test__floatundixf(0x8000008000000000ULL, 0x8.000008p+60))
73 if (test__floatundixf(0x8000000000000800ULL, 0x8.0000000000008p+60))
75 if (test__floatundixf(0x8000010000000000ULL, 0x8.00001p+60))
77 if (test__floatundixf(0x8000000000001000ULL, 0x8.000000000001p+60))
82 if (test__floatundixf(0x8000000000000001ULL, 0x8.000000000000001p+60L))
112 if (test__floatundixf(0x023479FD0E092DA1ULL, 0x8.D1E7F43824B684p+54L))
114 if (test__floatundixf(0x023479FD0E092DB0ULL, 0x8.D1E7f43824B6Cp+54L))
116 if (test__floatundixf(0x023479FD0E092DB8ULL, 0x8.D1E7F43824B6Ep+54L))
118 if (test__floatundixf(0x023479FD0E092DB6ULL, 0x8.D1E7F43824B6D8p+54L))
120 if (test__floatundixf(0x023479FD0E092DBFULL, 0x8.D1E7F43824B6FCp+54L)
    [all...]
floatdixf_test.c 111 if (test__floatdixf(0x023479FD0E092DA1LL, 0x8.D1E7F43824B684p+54L))
113 if (test__floatdixf(0x023479FD0E092DB0LL, 0x8.D1E7f43824B6Cp+54L))
115 if (test__floatdixf(0x023479FD0E092DB8LL, 0x8.D1E7F43824B6Ep+54L))
117 if (test__floatdixf(0x023479FD0E092DB6LL, 0x8.D1E7F43824B6D8p+54L))
119 if (test__floatdixf(0x023479FD0E092DBFLL, 0x8.D1E7F43824B6FCp+54L))
121 if (test__floatdixf(0x023479FD0E092DC1LL, 0x8.D1E7F43824B704p+54L))
123 if (test__floatdixf(0x023479FD0E092DC7LL, 0x8.D1E7F43824B71Cp+54L))
125 if (test__floatdixf(0x023479FD0E092DC8LL, 0x8.D1E7F43824B72p+54L))
127 if (test__floatdixf(0x023479FD0E092DCFLL, 0x8.D1E7F43824B73Cp+54L))
129 if (test__floatdixf(0x023479FD0E092DD0LL, 0x8.D1E7F43824B74p+54L)
    [all...]
  /src/sys/arch/hp300/dev/
rtcreg.h 46 #define RTC_REG5_24HR 0x8
  /src/bin/pax/
pat_rep.h 49 #define SYML 0x8
  /src/sys/external/gpl2/dts/dist/include/dt-bindings/sound/
adi,adau1977.h 15 #define ADAU1977_MICBIAS_9V0 0x8
  /src/sys/external/bsd/compiler_rt/dist/lib/sanitizer_common/
sanitizer_syscall_linux_aarch64.inc 17 register u64 x8 asm("x8") = nr;
21 : "r"(x8)
29 register u64 x8 asm("x8") = nr;
33 : "r"(x8), "0"(x0)
41 register u64 x8 asm("x8") = nr;
46 : "r"(x8), "0"(x0), "r"(x1)
54 register u64 x8 asm("x8") = nr
    [all...]
  /src/sys/arch/mac68k/obio/
grf_obioreg.h 94 #define VALKYRIE_CMAP_LEN 0x8
106 #define RBV_CMAP_CNTL 0x8
  /src/sys/compat/linux/arch/aarch64/
linux_sigcode.S 39 mov x8, #LINUX_SYS_rt_sigreturn
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
gmc_8_1_sh_mask.h 35 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
46 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
51 #define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
58 #define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
67 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
78 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
108 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
143 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
154 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
202 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
    [all...]
gmc_7_1_sh_mask.h 35 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
46 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
55 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
66 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
96 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
125 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
136 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
184 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
206 #define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
214 #define MC_ARB_PERF_CID__CH1__SHIFT 0x8
    [all...]
  /src/sys/arch/mvmeppc/stand/libsa/
bugsyscalls.S 63 li %r4,0x8
77 li %r4,0x8
91 li %r4,0x8
105 li %r4,0x8
  /src/sys/arch/sun2/sun2/
control.h 60 #define CONTEXT_NUM 0x8
  /src/sys/dev/i2c/
mpl115areg.h 45 #define MPL115A_B2_MSB 0x8
  /src/sys/dev/pci/
pciide_geode_reg.h 28 #define CS5530_PIO_REG(chan, drv) (0x20 + (chan) * 0x10 + (drv) * 0x8)
29 #define CS5530_DMA_REG(chan, drv) (0x24 + (chan) * 0x10 + (drv) * 0x8)
47 #define SC1100_PIO_REG(chan, drv) (0x40 + (chan) * 0x10 + (drv) * 0x8)
48 #define SC1100_DMA_REG(chan, drv) (0x44 + (chan) * 0x10 + (drv) * 0x8)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
stingray-pcie.dtsi 21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
27 <0x120 &gic_its 0x21d8 0x8>, /* PF3-VF24-31 */
29 <0x128 &gic_its 0x2260 0x8>, /* PF4-VF32-39 */
31 <0x130 &gic_its 0x22e8 0x8>, /* PF5-VF40-47 */
33 <0x138 &gic_its 0x2370 0x8>, /* PF6-VF48-55 */
35 <0x140 &gic_its 0x23f8 0x8>; /* PF7-VF56-63 */
  /src/sys/external/bsd/drm2/dist/drm/vmwgfx/
vmwgfx_reg.h 41 #define VMWGFX_IRQSTATUS_PORT 0x8
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vce/
vce_2_0_sh_mask.h 34 #define VCE_STATUS__UENC_BUSY__SHIFT 0x8
79 #define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x8
81 #define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x8
83 #define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x8
88 #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
bif_4_1_sh_mask.h 45 #define BUS_CNTL__PMI_MEM_DIS_MASK 0x8
56 #define BUS_CNTL__BIF_ERR_RTR_BKPRESSURE_EN__SHIFT 0x8
95 #define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK 0x8
103 #define HW_DEBUG__HW_03_DEBUG_MASK 0x8
114 #define HW_DEBUG__HW_08_DEBUG__SHIFT 0x8
183 #define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK 0x8
188 #define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8
201 #define BIF_DEBUG_CNTL__DEBUG_PAD_SEL_MASK 0x8
212 #define BIF_DEBUG_CNTL__DEBUG_IDSEL_BLK1__SHIFT 0x8
222 #define BIF_DEBUG_MUX__DEBUG_MUX_BLK2__SHIFT 0x8
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
smu_7_0_0_sh_mask.h 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
48 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
60 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
72 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
83 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
94 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
109 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
188 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
198 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
215 #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
    [all...]

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