Searched refs:GEN5_PIPE_CONTROL_DEPTH_CACHE_FLUSH (Results 1 - 2 of 2) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen5_render.h202 #define GEN5_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen5_render.h202 #define GEN5_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) macro

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