Searched refs:GLC (Results 1 - 4 of 4) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/mesa/main/
H A Dextensions_table.h4 #define GLC 0 macro
9 EXT(3DFX_texture_compression_FXT1 , TDFX_texture_compression_FXT1 , GLL, GLC, x , x , 1999)
12 EXT(AMD_conservative_depth , ARB_conservative_depth , GLL, GLC, x , x , 2009)
13 EXT(AMD_depth_clamp_separate , AMD_depth_clamp_separate , GLL, GLC, x , x , 2009)
14 EXT(AMD_draw_buffers_blend , ARB_draw_buffers_blend , GLL, GLC, x , x , 2009)
15 EXT(AMD_framebuffer_multisample_advanced , AMD_framebuffer_multisample_advanced , GLL, GLC, x , ES2, 2018)
16 EXT(AMD_gpu_shader_int64 , ARB_gpu_shader_int64 , x , GLC, x , x , 2015)
17 EXT(AMD_multi_draw_indirect , ARB_draw_indirect , GLL, GLC, x , x , 2011)
18 EXT(AMD_performance_monitor , AMD_performance_monitor , GLL, GLC, x , ES2, 2007)
19 EXT(AMD_pinned_memory , AMD_pinned_memory , GLL, GLC,
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/mesa/main/
H A Dextensions_table.h4 #define GLC 0 macro
9 EXT(3DFX_texture_compression_FXT1 , TDFX_texture_compression_FXT1 , GLL, GLC, x , x , 1999)
12 EXT(AMD_conservative_depth , ARB_conservative_depth , GLL, GLC, x , x , 2009)
13 EXT(AMD_depth_clamp_separate , AMD_depth_clamp_separate , GLL, GLC, x , x , 2009)
14 EXT(AMD_draw_buffers_blend , ARB_draw_buffers_blend , GLL, GLC, x , x , 2009)
15 EXT(AMD_framebuffer_multisample_advanced , AMD_framebuffer_multisample_advanced , GLL, GLC, x , ES2, 2018)
16 EXT(AMD_gpu_shader_int64 , ARB_gpu_shader_int64 , x , GLC, x , x , 2015)
17 EXT(AMD_multi_draw_indirect , ARB_draw_indirect , GLL, GLC, x , x , 2011)
18 EXT(AMD_performance_monitor , AMD_performance_monitor , GLL, GLC, x , ES2, 2007)
19 EXT(AMD_pinned_memory , AMD_pinned_memory , GLL, GLC,
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A DREADME-ISA.md126 ## RDNA L0, L1 cache and DLC, GLC bits
130 GLC bits that interact with the cache.
133 * GLC ("globally coherent") bit: controls the L0 cache
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D19.0.0.rst2004 - amd/common/vi+: enable SMEM loads with GLC=1

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