Searched refs:smul (Results 1 - 7 of 7) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/
H A Dmidgard_schedule.c1005 * always scalar, so it is always in smul (exception: ball/bany, which
1096 midgard_instruction **smul,
1108 midgard_instruction **units[] = { smul, vadd, vlut };
1177 midgard_instruction *smul = NULL; local in function:mir_schedule_alu
1191 smul = cond;
1198 * smul */
1216 * This prevents csel and csel_v being scheduled into smul
1256 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, false);
1259 mir_schedule_zs_write(ctx, &predicate, instructions, liveness, worklist, len, branch, &smul, &vadd, &vlut, true);
1261 mir_choose_alu(&smul, instruction
1089 mir_schedule_zs_write(compiler_context * ctx,struct midgard_predicate * predicate,midgard_instruction ** instructions,uint16_t * liveness,BITSET_WORD * worklist,unsigned len,midgard_instruction * branch,midgard_instruction ** smul,midgard_instruction ** vadd,midgard_instruction ** vlut,bool stencil) argument
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/xsrc/external/mit/MesaLib.old/dist/src/compiler/spirv/
H A Dvtn_alu.c479 nir_ssa_def *smul = nir_imul_2x32_64(&b->nb, src[0], src[1]); local in function:vtn_handle_alu
480 val->ssa->elems[0]->def = nir_unpack_64_2x32_split_x(&b->nb, smul);
481 val->ssa->elems[1]->def = nir_unpack_64_2x32_split_y(&b->nb, smul);
/xsrc/external/mit/MesaLib/dist/src/compiler/spirv/
H A Dvtn_alu.c541 nir_ssa_def *smul = nir_imul_2x32_64(&b->nb, src[0], src[1]); local in function:vtn_handle_alu
542 dest->elems[0]->def = nir_unpack_64_2x32_split_x(&b->nb, smul);
543 dest->elems[1]->def = nir_unpack_64_2x32_split_y(&b->nb, smul);
/xsrc/external/mit/xf86-video-sunffb/dist/src/
H A DVISmoveImage.s88 #define SMUL smul
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D19.3.0.rst368 - pan/midgard: Schedule to smul/sadd
H A D19.1.0.rst430 - panfrost/midgard: Promote smul to vmul
H A D20.2.0.rst658 - pan/mdg: Defer smul, vlut until after writeout moves

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