| /xsrc/external/mit/libdrm/dist/radeon/ |
| radeon_cs.h | 123 static inline void radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword)
125 memcpy(cs->packets + cs->cdw, &qword, sizeof(uint64_t));
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| /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/ |
| mir_promote_uniforms.c | 292 unsigned qword = ins->constants.u32[0] / 16; local
305 if (!BITSET_TEST(analysis.blocks[ubo].pushed, qword)) {
311 unsigned base = pan_lookup_pushed_ubo(&ctx->info->push, ubo, qword * 16);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/virgl/ |
| virgl_encode.h | 63 uint64_t qword)
65 memcpy(state->buf + state->cdw, &qword, sizeof(uint64_t));
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| virgl_encode.c | 338 uint64_t qword; local
340 STATIC_ASSERT(sizeof(qword) == sizeof(depth));
341 memcpy(&qword, &depth, sizeof(qword));
347 virgl_encoder_write_qword(ctx->cbuf, qword);
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| /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/ |
| genX_query.c | 390 for (uint32_t qword = 1; qword < (pool->stride / 8); qword++) {
392 anv_address_add(slot_addr, qword * 8),
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/virgl/ |
| virgl_encode.h | 64 uint64_t qword)
66 memcpy(state->buf + state->cdw, &qword, sizeof(uint64_t));
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| virgl_encode.c | 604 uint64_t qword; local
606 STATIC_ASSERT(sizeof(qword) == sizeof(depth));
607 memcpy(&qword, &depth, sizeof(qword));
613 virgl_encoder_write_qword(ctx->cbuf, qword);
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| /xsrc/external/mit/xf86-video-intel/dist/src/sna/ |
| sna_render_inline.h | 68 static force_inline void batch_emit64(struct sna *sna, uint64_t qword)
72 *(uint64_t *)(sna->kgem.batch+sna->kgem.nbatch) = qword;
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| /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/ |
| sna_render_inline.h | 59 static force_inline void batch_emit64(struct sna *sna, uint64_t qword)
63 *(uint64_t *)(sna->kgem.batch+sna->kgem.nbatch) = qword;
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| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| tu_query.c | 814 A6XX_RB_SAMPLE_COUNT_ADDR(.qword = begin_iova));
935 tu_cs_emit_regs(cs, A6XX_VPC_SO_STREAM_COUNTS(.qword = begin_iova));
1029 A6XX_RB_SAMPLE_COUNT_ADDR(.qword = end_iova));
1213 tu_cs_emit_regs(cs, A6XX_VPC_SO_STREAM_COUNTS(.qword = end_iova));
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| tu_clear_blit.c | 196 A6XX_SP_PS_2D_SRC(.qword = va),
230 A6XX_RB_2D_DST(.qword = va),
840 tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_SAMP(.qword = texture.iova + A6XX_TEX_CONST_DWORDS * 4));
850 tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
964 A6XX_RB_MRT_BASE(0, .qword = va),
2785 A6XX_SP_PS_2D_SRC(.qword = cmd->device->physical_device->gmem_base + gmem_offset),
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| tu_cmd_buffer.c | 1139 tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
1685 A6XX_VFD_FETCH_BASE(i, .qword = cmd->state.vb[i].base),
3951 tu_cs_emit_regs(cs, A6XX_PC_TESSFACTOR_ADDR(.qword = tess_factor_iova));
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| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| genX_query.c | 667 for (uint32_t qword = 1; qword < (pool->stride / 8); qword++) {
669 anv_address_add(slot_addr, qword * 8),
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| /xsrc/external/mit/MesaLib/dist/src/freedreno/decode/ |
| cffdec.c | 404 reg_dump_gpuaddr64(const char *name, uint64_t qword, int level)
406 dump_gpuaddr(qword, level);
474 reg_disasm_gpuaddr64(const char *name, uint64_t qword, int level)
476 disasm_gpuaddr(name, qword, level);
545 void (*fxn64)(const char *name, uint64_t qword, int level);
878 uint64_t qword = (((uint64_t)reg_val(regbase + 1)) << 32) | dword; local
879 type0_reg[idx].fxn64(type0_reg[idx].regname, qword, level);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/zink/nir_to_spirv/ |
| nir_to_spirv.c | 2234 bool qword = bit_size == 64; local
2244 for (unsigned j = 0; j < 1 + !!qword; j++) {
2250 if (qword)
2267 bool qword = nir_src_bit_size(intr->src[0]) == 64; local
2280 for (unsigned j = 0; j < 1 + !!qword; j++) {
2281 unsigned comp = ((1 + !!qword) * i) + j;
2284 if (nir_src_num_components(intr->src[0]) != 1 || qword)
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| /xsrc/external/mit/MesaLib/dist/src/mesa/x86/ |
| assyntax.h | 894 #define QWORD_PTR qword
937 #define QWORD_PTR qword ptr
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/x86/ |
| assyntax.h | 894 #define QWORD_PTR qword
937 #define QWORD_PTR qword ptr
|
