Searched full:pstate (Results 1 - 25 of 89) sorted by relevance

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/src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvif/
H A Dif0001.h16 __s8 ustate_ac; /* out: target pstate index */
17 __s8 ustate_dc; /* out: target pstate index */
21 __s8 pstate; /* out: current pstate index */ member in struct:nvif_control_pstate_info_v0
28 __s8 state; /* in: index of pstate to query
29 * out: pstate identifier
45 __s8 ustate; /* in: pstate identifier */
/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/
H A Dnouveau_nvkm_subdev_clk_base.c47 u8 pstate, u8 domain, u32 input)
54 data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
117 nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate, argument
124 if (!pstate || !cstate)
141 list_for_each_entry_from_reverse(cstate, &pstate->list, head) {
150 nvkm_cstate_get(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) argument
154 return list_last_entry(&pstate->list, typeof(*cstate), head);
156 list_for_each_entry(cstate, &pstate->list, head) {
165 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) argument
174 if (!list_empty(&pstate
46 nvkm_clk_adjust(struct nvkm_clk * clk,bool adjust,u8 pstate,u8 domain,u32 input) argument
228 nvkm_cstate_new(struct nvkm_clk * clk,int idx,struct nvkm_pstate * pstate) argument
275 struct nvkm_pstate *pstate; local in function:nvkm_pstate_prog
307 int pstate; local in function:nvkm_pstate_work
378 nvkm_pstate_info(struct nvkm_clk * clk,struct nvkm_pstate * pstate) argument
421 nvkm_pstate_del(struct nvkm_pstate * pstate) argument
438 struct nvkm_pstate *pstate; local in function:nvkm_pstate_new
507 struct nvkm_pstate *pstate; local in function:nvkm_clk_ustate_update
660 struct nvkm_pstate *pstate, *temp; local in function:nvkm_clk_dtor
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/src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/bios/
H A Dcstep.h10 u8 pstate; member in struct:nvbios_cstepE
17 u32 nvbios_cstepEm(struct nvkm_bios *, u8 pstate, u8 *ver, u8 *hdr,
H A Dvpstate.h21 u8 pstate; member in struct:nvbios_vpstate_entry
H A Dboost.h9 u8 pstate; member in struct:nvbios_boostE
H A Dperf.h10 u8 pstate; member in struct:nvbios_perfE
/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/device/
H A Dnouveau_nvkm_engine_device_ctrl.c48 nvif_ioctl(&ctrl->object, "control pstate info size %d\n", size);
50 nvif_ioctl(&ctrl->object, "control pstate info vers %d\n",
60 args->v0.pstate = clk->pstate;
66 args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN;
80 struct nvkm_pstate *pstate; local in function:nvkm_control_mthd_pstate_attr
86 nvif_ioctl(&ctrl->object, "control pstate attr size %d\n", size);
89 "control pstate attr vers %d state %d index %d\n",
111 list_for_each_entry(pstate, &clk->states, head) {
116 lo = pstate
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_hubbub.c129 /* pstate latency is ~20us so if we wait over 40us and pstate allow
133 * pstate takes around ~100us on linux. Unknown currently as to
145 /* we hacked to force pstate allow to prevent hang last time
158 * 0: Pipe0 Plane0 Allow Pstate Change
159 * 1: Pipe0 Plane1 Allow Pstate Change
160 * 2: Pipe0 Cursor0 Allow Pstate Change
161 * 3: Pipe0 Cursor1 Allow Pstate Change
162 * 4: Pipe1 Plane0 Allow Pstate Change
163 * 5: Pipe1 Plane1 Allow Pstate Chang
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/src/sys/arch/sparc/stand/ofwboot/
H A Dsrt0.s102 wrpr %g0, PSTATE_PRIV+PSTATE_IE, %pstate
158 rdpr %pstate, %l0
160 wrpr %g0, PSTATE_PROM|PSTATE_IE, %pstate
161 wrpr %l0, %g0, %pstate
176 rdpr %pstate, %l0
188 wrpr %g0, PSTATE_PROM|PSTATE_IE, %pstate ! Enable 64-bit addresses for the prom
189 wrpr %l0, 0, %pstate
278 rdpr %pstate, %o4
279 wrpr %o4, PSTATE_IE, %pstate
285 wrpr %o4, 0, %pstate
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/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_xgmi.c281 tmp->pstate = -1;
287 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) argument
293 bool is_high_pstate = pstate && adev->asic_type == CHIP_VEGA20;
300 if (hive->pstate == pstate) {
301 adev->pstate = is_high_pstate ? pstate : adev->pstate;
305 dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
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H A Damdgpu_xgmi.h40 int pstate; /*0 -- low , 1 -- high , -1 unknown*/ member in struct:amdgpu_hive_info
48 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
/src/sys/external/bsd/drm2/dist/drm/nouveau/include/nvkm/subdev/
H A Dclk.h13 #define NVKM_CLK_CSTATE_BASE -2 /* pstate base */
69 u8 pstate; member in struct:nvkm_pstate
106 int pstate; /* current */ member in struct:nvkm_clk
/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bios/
H A Dnouveau_nvkm_subdev_bios_boost.c86 info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5;
94 nvbios_boostEm(struct nvkm_bios *bios, u8 pstate, argument
99 if (info->pstate == pstate)
H A Dnouveau_nvkm_subdev_bios_cstep.c83 info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5;
90 nvbios_cstepEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr, argument
95 if (info->pstate == pstate)
/src/sys/arch/sparc64/include/
H A Dctlreg.h301 #define SFSR_PRIV 0x00008 /* value of PSTATE.PRIV for faulting access */
527 "rdpr %%pstate,%1; " \
529 "wrpr %1,8,%%pstate; " \
533 "wrpr %1,0,%%pstate " \
547 "rdpr %%pstate,%1; " \
549 "wrpr %1,8,%%pstate; " \
553 "wrpr %1,0,%%pstate; " \
579 "rdpr %%pstate,%1; " \
581 "wrpr %1,8,%%pstate; " \
584 "wrpr %1,0,%%pstate; " \
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H A Dnetbsd32_machdep.h53 int sc_psr; /* pstate to restore */
66 int sc_psr; /* pstate to restore */
H A Dpsl.h107 * SPARC V9 PSTATE register (what replaces the PSR in V9)
171 * | CCR | ASI | - | PSTATE | - | CWP |
378 SPARC64_RDPR_DEF(pstate, %pstate, int) /* getpstate() */
379 SPARC64_WRPR_DEF(pstate, %pstate, int) /* setpstate() */
413 int pstate = getpstate(); variable in typeref:typename:int
415 setpstate(pstate & ~PSTATE_IE);
416 return pstate;
420 intr_restore(int pstate) argument
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/src/sys/arch/arm/apple/
H A Dapple_pmgr.c73 const uint32_t pstate = enable ? PMGR_PS_ACTIVE : PMGR_PS_PWRGATE; local in function:apple_pmgr_enable
88 val |= __SHIFTIN(pstate, PMGR_PS_TARGET_MASK);
93 if (__SHIFTOUT(val, PMGR_PS_ACTUAL_MASK) == pstate)
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddm_pp_smu.h32 * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
234 * to perform pstate handshaking in its current state. Typically this handshake
235 * is used to perform uCLK switching, so disabling pstate disables uCLK switching.
238 * DC will make the call BEFORE setting up the display state which would cause pstate
/src/sys/arch/sparc64/doc/
H A DTODO35 - replace constructs like "wrpr %g0, PSTATE_KERN, %pstate" with NORMAL_GLOBALS
36 - replace constructs line "wrpr %g0, PSTATE_INTR, %pstate" with ALTERNATE_GOBALS
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Drenoir_ppt.h30 /* UMD PState Renoir Msg Parameters in MHz */
/src/sys/external/bsd/drm2/amdgpu/
H A Damdgpu_xgmi.c62 amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) argument
/src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/
H A Dnouveau_nvkm_subdev_pmu_gk20a.c68 *state = clk->pstate;
79 /* For GK20A, the performance level is directly mapped to pstate */
80 level = cur_level = clk->pstate;
/src/sys/net/agr/
H A Dieee8023ad_lacp_sm_rx.c177 LACP_DPRINTF((lp, "old pstate %s\n",
179 LACP_DPRINTF((lp, "new pstate %s\n",
/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_mmhubbub.c64 * unsigned int pstate_watermark[4]; //4 group pstate watermark
182 /* Programming nb pstate watermark */
242 /* set which group of pstate watermark to use and set wbif watermark change request */

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