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    Searched refs:R4030 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arc/jazz/
pica.h	62 #define R4030 R4030_V_LOCAL_IO_BASE 64 #define R4030_SYS_CONFIG (R4030+0x0000) /* Global config register */ 65 #define R4030_SYS_TL_BASE (R4030+0x0018) /* DMA transl. table base */ 66 #define R4030_SYS_TL_LIMIT (R4030+0x0020) /* DMA transl. table limit */ 67 #define R4030_SYS_TL_IVALID (R4030+0x0028) /* DMA transl. cache inval */ 68 #define R4030_SYS_DMA0_REGS (R4030+0x0100) /* DMA ch0 base address */ 69 #define R4030_SYS_DMA1_REGS (R4030+0x0120) /* DMA ch0 base address */ 70 #define R4030_SYS_DMA2_REGS (R4030+0x0140) /* DMA ch0 base address */ 71 #define R4030_SYS_DMA3_REGS (R4030+0x0160) /* DMA ch0 base address */ 72 #define R4030_SYS_DMA_INT_SRC (R4030+0x0200) /* DMA int source status reg *     [all...]
pica.h	62 #define R4030 R4030_V_LOCAL_IO_BASE 64 #define R4030_SYS_CONFIG (R4030+0x0000) /* Global config register */ 65 #define R4030_SYS_TL_BASE (R4030+0x0018) /* DMA transl. table base */ 66 #define R4030_SYS_TL_LIMIT (R4030+0x0020) /* DMA transl. table limit */ 67 #define R4030_SYS_TL_IVALID (R4030+0x0028) /* DMA transl. cache inval */ 68 #define R4030_SYS_DMA0_REGS (R4030+0x0100) /* DMA ch0 base address */ 69 #define R4030_SYS_DMA1_REGS (R4030+0x0120) /* DMA ch0 base address */ 70 #define R4030_SYS_DMA2_REGS (R4030+0x0140) /* DMA ch0 base address */ 71 #define R4030_SYS_DMA3_REGS (R4030+0x0160) /* DMA ch0 base address */ 72 #define R4030_SYS_DMA_INT_SRC (R4030+0x0200) /* DMA int source status reg *     [all...]

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Indexes created Sun Mar 01 05:31:48 UTC 2026