| /src/sys/arch/arm/nvidia/ |
| tegra_clock.h | 50 u_int base_reg; member in struct:tegra_pll_clk
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| tegra_clock.h | 50 u_int base_reg; member in struct:tegra_pll_clk
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| tegra210_car.c | 314 .base_reg = (_base), \
1158 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1161 if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1163 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) {
1166 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) {
1194 if (tpll->base_reg == CAR_PLLX_BASE_REG) {
1221 base = bus_space_read_4(bst, bsh, tpll->base_reg);
1234 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) {
1240 tegra_reg_set_clear(bst, bsh, tpll->base_reg,
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| tegra210_car.c | 314 .base_reg = (_base), \
1158 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1161 if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1163 } else if (tpll->base_reg == CAR_PLLP_BASE_REG) {
1166 } else if (tpll->base_reg == CAR_PLLE_BASE_REG) {
1194 if (tpll->base_reg == CAR_PLLX_BASE_REG) {
1221 base = bus_space_read_4(bst, bsh, tpll->base_reg);
1234 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) {
1240 tegra_reg_set_clear(bst, bsh, tpll->base_reg,
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| tegra124_car.c | 302 .base_reg = (_base), \
1036 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1039 if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1066 if (tpll->base_reg == CAR_PLLX_BASE_REG) {
1093 base = bus_space_read_4(bst, bsh, tpll->base_reg);
1106 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) {
1112 tegra_reg_set_clear(bst, bsh, tpll->base_reg,
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| tegra124_car.c | 302 .base_reg = (_base), \
1036 const uint32_t base = bus_space_read_4(bst, bsh, tpll->base_reg);
1039 if (tpll->base_reg == CAR_PLLU_BASE_REG) {
1066 if (tpll->base_reg == CAR_PLLX_BASE_REG) {
1093 base = bus_space_read_4(bst, bsh, tpll->base_reg);
1106 } else if (tpll->base_reg == CAR_PLLD2_BASE_REG) {
1112 tegra_reg_set_clear(bst, bsh, tpll->base_reg,
|
| /src/sys/arch/x86/pci/ |
| ichlpcib.c | 880 int pin, shift, base_reg, cntl_reg, reg; local in function:lpcib_gpio_configure
888 base_reg = LPCIB_PCI_GPIO_BASE_ICH6;
891 base_reg = LPCIB_PCI_GPIO_BASE;
909 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg);
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| ichlpcib.c | 880 int pin, shift, base_reg, cntl_reg, reg; local in function:lpcib_gpio_configure
888 base_reg = LPCIB_PCI_GPIO_BASE_ICH6;
891 base_reg = LPCIB_PCI_GPIO_BASE;
909 reg = pci_conf_read(sc->sc_pa.pa_pc, sc->sc_pa.pa_tag, base_reg);
|
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeARM_32.c | 861 #define EMIT_DATA_TRANSFER(type, add, wb, target_reg, base_reg, arg) \
862 (data_transfer_insts[(type) & 0xf] | ((add) << 23) | ((wb) << (21 - 4)) | (reg_map[target_reg] << 12) | (reg_map[base_reg] << 16) | (arg))
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| sljitNativeARM_32.c | 861 #define EMIT_DATA_TRANSFER(type, add, wb, target_reg, base_reg, arg) \
862 (data_transfer_insts[(type) & 0xf] | ((add) << 23) | ((wb) << (21 - 4)) | (reg_map[target_reg] << 12) | (reg_map[base_reg] << 16) | (arg))
|
